diff mbox series

[v2,2/2] net/cnxk: add support for rte flow item raw

Message ID 20210706101259.1598009-2-psatheesh@marvell.com (mailing list archive)
State Superseded, archived
Delegated to: Jerin Jacob
Headers show
Series [v2,1/2] common/cnxk: add support for rte flow item raw | expand

Checks

Context Check Description
ci/Intel-compilation warning apply issues
ci/checkpatch success coding style OK

Commit Message

Satheesh Paul July 6, 2021, 10:12 a.m. UTC
From: Satheesh Paul <psatheesh@marvell.com>

Add support for rte_flow_item_raw to parse custom L2 and L3 protocols.

Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Reviewed-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>
---
 doc/guides/nics/cnxk.rst               | 37 +++++++++++++++++++++++++-
 drivers/net/cnxk/cnxk_ethdev_devargs.c |  7 +++++
 drivers/net/cnxk/cnxk_rte_flow.c       | 12 ++++-----
 3 files changed, 49 insertions(+), 7 deletions(-)
diff mbox series

Patch

diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst
index cb2a51e1d..90d27dbaa 100644
--- a/doc/guides/nics/cnxk.rst
+++ b/doc/guides/nics/cnxk.rst
@@ -165,7 +165,7 @@  Runtime Config Options
 
    With the above configuration, higig2 will be enabled on that port and the
    traffic on this port should be higig2 traffic only. Supported switch header
-   types are "higig2", "dsa", "chlen90b" and "chlen24b".
+   types are "chlen24b", "chlen90b", "dsa", "exdsa", "higig2" and "vlan_exdsa".
 
 - ``RSS tag as XOR`` (default ``0``)
 
@@ -215,6 +215,41 @@  RTE flow GRE support
 - ``RTE_FLOW_ITEM_TYPE_GRE_KEY`` works only when checksum and routing
   bits in the GRE header are equal to 0.
 
+Custom protocols supported in RTE Flow
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The ``RTE_FLOW_ITEM_TYPE_RAW`` can be used to parse the below custom protocols.
+
+* ``vlan_exdsa`` and ``exdsa`` can be parsed at L2 level.
+* ``NGIO`` can be parsed at L3 level.
+
+For ``vlan_exdsa`` and ``exdsa``, the port has to be configured with the
+respective switch header.
+
+For example::
+
+   -a 0002:02:00.0,switch_header="vlan_exdsa"
+
+The below fields of ``struct rte_flow_item_raw`` shall be used to specify the
+pattern.
+
+- ``relative`` Selects the layer at which parsing is done.
+
+  - 0 for ``exdsa`` and ``vlan_exdsa``.
+
+  - 1 for  ``NGIO``.
+
+- ``offset`` The offset in the header where the pattern should be matched.
+- ``length`` Length of the pattern.
+- ``pattern`` Pattern as a byte string.
+
+Example usage in testpmd::
+
+   ./dpdk-testpmd -c 3 -w 0002:02:00.0,switch_header=exdsa -- -i \
+                  --rx-offloads=0x00080000 --rxq 8 --txq 8
+   testpmd> flow create 0 ingress pattern eth / raw relative is 0 pattern \
+          spec ab pattern mask ab offset is 4 / end actions queue index 1 / end
+
 Debugging Options
 -----------------
 
diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c
index c76b6281c..36b437a18 100644
--- a/drivers/net/cnxk/cnxk_ethdev_devargs.c
+++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c
@@ -99,6 +99,13 @@  parse_switch_header_type(const char *key, const char *value, void *extra_args)
 
 	if (strcmp(value, "chlen90b") == 0)
 		*(uint16_t *)extra_args = ROC_PRIV_FLAGS_LEN_90B;
+
+	if (strcmp(value, "exdsa") == 0)
+		*(uint16_t *)extra_args = ROC_PRIV_FLAGS_EXDSA;
+
+	if (strcmp(value, "vlan_exdsa") == 0)
+		*(uint16_t *)extra_args = ROC_PRIV_FLAGS_VLAN_EXDSA;
+
 	return 0;
 }
 
diff --git a/drivers/net/cnxk/cnxk_rte_flow.c b/drivers/net/cnxk/cnxk_rte_flow.c
index 213125b56..32c1b5dee 100644
--- a/drivers/net/cnxk/cnxk_rte_flow.c
+++ b/drivers/net/cnxk/cnxk_rte_flow.c
@@ -15,8 +15,8 @@  const struct cnxk_rte_flow_term_info term[] = {
 	[RTE_FLOW_ITEM_TYPE_IPV6] = {ROC_NPC_ITEM_TYPE_IPV6,
 				     sizeof(struct rte_flow_item_ipv6)},
 	[RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4] = {
-		ROC_NPC_ITEM_TYPE_ARP_ETH_IPV4,
-		sizeof(struct rte_flow_item_arp_eth_ipv4)},
+			ROC_NPC_ITEM_TYPE_ARP_ETH_IPV4,
+			sizeof(struct rte_flow_item_arp_eth_ipv4)},
 	[RTE_FLOW_ITEM_TYPE_MPLS] = {ROC_NPC_ITEM_TYPE_MPLS,
 				     sizeof(struct rte_flow_item_mpls)},
 	[RTE_FLOW_ITEM_TYPE_ICMP] = {ROC_NPC_ITEM_TYPE_ICMP,
@@ -50,10 +50,10 @@  const struct cnxk_rte_flow_term_info term[] = {
 	[RTE_FLOW_ITEM_TYPE_ANY] = {ROC_NPC_ITEM_TYPE_ANY, 0},
 	[RTE_FLOW_ITEM_TYPE_GRE_KEY] = {ROC_NPC_ITEM_TYPE_GRE_KEY,
 					sizeof(uint32_t)},
-	[RTE_FLOW_ITEM_TYPE_HIGIG2] = {
-		ROC_NPC_ITEM_TYPE_HIGIG2,
-		sizeof(struct rte_flow_item_higig2_hdr)}
-};
+	[RTE_FLOW_ITEM_TYPE_HIGIG2] = {ROC_NPC_ITEM_TYPE_HIGIG2,
+				       sizeof(struct rte_flow_item_higig2_hdr)},
+	[RTE_FLOW_ITEM_TYPE_RAW] = {ROC_NPC_ITEM_TYPE_RAW,
+				    sizeof(struct rte_flow_item_raw)}};
 
 static int
 npc_rss_action_validate(struct rte_eth_dev *eth_dev,