From patchwork Mon Jul 5 04:09:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Satheesh Paul Antonysamy X-Patchwork-Id: 95255 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5DC41A0A0F; Mon, 5 Jul 2021 06:10:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BF9E641140; Mon, 5 Jul 2021 06:09:59 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 311EE4113F for ; Mon, 5 Jul 2021 06:09:58 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 16541JjL026578 for ; Sun, 4 Jul 2021 21:09:57 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=HAbc9TmkFmvvh559eTgiYwKC4x0jtnDhX50S0qfwxSs=; b=TxY5vcckO4578bQe5qvXJHgRGslhih1c9iPRERy8LOvpieCu7Vjf8eWFapxlLNjxkqlA 6TD7ATyT4MMrXbxbKZhwyx4963MDrwYW/NR2Q11N2yex5xwKi6C2aYsRGX0mCHw3tr/d iW6pmIedG8NJgor122HxOt+/dbJTdzXzawHX0inbjUujVFBJoiQQLtr7SCCPaRX6lOWV 5I8CxF4OoD5W0GLYe2IBkrF+yoyl/iicuOudq48kGD7Sx+0xvScJapoldm3k65huVSWc CjzA6YHFGWXlaSSlqfFRV0qSm8WSwbbScpWz1ikOx08h1M/1g0XT3gTutm2vsWm48NKY yw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 39kt2m841x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sun, 04 Jul 2021 21:09:57 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 4 Jul 2021 21:09:55 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sun, 4 Jul 2021 21:09:55 -0700 Received: from localhost.localdomain (unknown [10.28.34.33]) by maili.marvell.com (Postfix) with ESMTP id 2EC9B5B6921; Sun, 4 Jul 2021 21:09:52 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Satheesh Paul Date: Mon, 5 Jul 2021 09:39:42 +0530 Message-ID: <20210705040942.1524345-2-psatheesh@marvell.com> X-Mailer: git-send-email 2.25.4 In-Reply-To: <20210705040942.1524345-1-psatheesh@marvell.com> References: <20210705040942.1524345-1-psatheesh@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 8G-MlvE5KkLbdcsiY9L5vqZs7F7yDJFB X-Proofpoint-GUID: 8G-MlvE5KkLbdcsiY9L5vqZs7F7yDJFB X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-05_03:2021-07-02, 2021-07-05 signatures=0 Subject: [dpdk-dev] [PATCH 2/2] net/cnxk: add support for rte flow item raw X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Satheesh Paul Add support for rte_flow_item_raw to parse custom L2 and L3 protocols. Signed-off-by: Satheesh Paul Reviewed-by: Kiran Kumar Kokkilagadda --- doc/guides/nics/cnxk.rst | 169 +++++++++++++++++++++++-- drivers/net/cnxk/cnxk_ethdev_devargs.c | 7 + drivers/net/cnxk/cnxk_rte_flow.c | 12 +- 3 files changed, 172 insertions(+), 16 deletions(-) diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst index cb2a51e1d..a7b59a48e 100644 --- a/doc/guides/nics/cnxk.rst +++ b/doc/guides/nics/cnxk.rst @@ -104,7 +104,7 @@ Runtime Config Options - ``Rx&Tx scalar mode enable`` (default ``0``) - PMD supports both scalar and vector mode, it may be selected at runtime + Ethdev supports both scalar and vector mode, it may be selected at runtime using ``scalar_enable`` ``devargs`` parameter. - ``RSS reta size`` (default ``64``) @@ -151,7 +151,7 @@ Runtime Config Options -a 0002:02:00.0,max_sqb_count=64 - With the above configuration, each send queue's descriptor buffer count is + With the above configuration, each send queue's decscriptor buffer count is limited to a maximum of 64 buffers. - ``Switch header enable`` (default ``none``) @@ -165,7 +165,7 @@ Runtime Config Options With the above configuration, higig2 will be enabled on that port and the traffic on this port should be higig2 traffic only. Supported switch header - types are "higig2", "dsa", "chlen90b" and "chlen24b". + types are "chlen24b", "chlen90b", "dsa", "exdsa", "higig2" and "vlan_exdsa". - ``RSS tag as XOR`` (default ``0``) @@ -186,6 +186,7 @@ Runtime Config Options -a 0002:02:00.0,tag_as_xor=1 + .. note:: Above devarg parameters are configurable per device, user needs to pass the @@ -196,7 +197,7 @@ Limitations ----------- ``mempool_cnxk`` external mempool handler dependency -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The OCTEON CN9K/CN10K SoC family NIC has inbuilt HW assisted external mempool manager. ``net_cnxk`` pmd only works with ``mempool_cnxk`` mempool handler @@ -209,12 +210,6 @@ CRC stripping The OCTEON CN9K/CN10K SoC family NICs strip the CRC for every packet being received by the host interface irrespective of the offload configuration. -RTE flow GRE support -~~~~~~~~~~~~~~~~~~~~ - -- ``RTE_FLOW_ITEM_TYPE_GRE_KEY`` works only when checksum and routing - bits in the GRE header are equal to 0. - Debugging Options ----------------- @@ -229,3 +224,157 @@ Debugging Options +---+------------+-------------------------------------------------------+ | 2 | NPC | --log-level='pmd\.net.cnxk\.flow,8' | +---+------------+-------------------------------------------------------+ + +RTE Flow Support +---------------- + +The OCTEON CN9K/CN10K SoC family NIC has support for the following patterns and +actions. + +Patterns: + +.. _table_cnxk_supported_flow_item_types: + +.. table:: Item types + + +----+--------------------------------+ + | # | Pattern Type | + +====+================================+ + | 1 | RTE_FLOW_ITEM_TYPE_ETH | + +----+--------------------------------+ + | 2 | RTE_FLOW_ITEM_TYPE_VLAN | + +----+--------------------------------+ + | 3 | RTE_FLOW_ITEM_TYPE_E_TAG | + +----+--------------------------------+ + | 4 | RTE_FLOW_ITEM_TYPE_IPV4 | + +----+--------------------------------+ + | 5 | RTE_FLOW_ITEM_TYPE_IPV6 | + +----+--------------------------------+ + | 6 | RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4| + +----+--------------------------------+ + | 7 | RTE_FLOW_ITEM_TYPE_MPLS | + +----+--------------------------------+ + | 8 | RTE_FLOW_ITEM_TYPE_ICMP | + +----+--------------------------------+ + | 9 | RTE_FLOW_ITEM_TYPE_UDP | + +----+--------------------------------+ + | 10 | RTE_FLOW_ITEM_TYPE_TCP | + +----+--------------------------------+ + | 11 | RTE_FLOW_ITEM_TYPE_SCTP | + +----+--------------------------------+ + | 12 | RTE_FLOW_ITEM_TYPE_ESP | + +----+--------------------------------+ + | 13 | RTE_FLOW_ITEM_TYPE_GRE | + +----+--------------------------------+ + | 14 | RTE_FLOW_ITEM_TYPE_NVGRE | + +----+--------------------------------+ + | 15 | RTE_FLOW_ITEM_TYPE_VXLAN | + +----+--------------------------------+ + | 16 | RTE_FLOW_ITEM_TYPE_GTPC | + +----+--------------------------------+ + | 17 | RTE_FLOW_ITEM_TYPE_GTPU | + +----+--------------------------------+ + | 18 | RTE_FLOW_ITEM_TYPE_GENEVE | + +----+--------------------------------+ + | 19 | RTE_FLOW_ITEM_TYPE_VXLAN_GPE | + +----+--------------------------------+ + | 20 | RTE_FLOW_ITEM_TYPE_IPV6_EXT | + +----+--------------------------------+ + | 21 | RTE_FLOW_ITEM_TYPE_VOID | + +----+--------------------------------+ + | 22 | RTE_FLOW_ITEM_TYPE_ANY | + +----+--------------------------------+ + | 23 | RTE_FLOW_ITEM_TYPE_GRE_KEY | + +----+--------------------------------+ + | 24 | RTE_FLOW_ITEM_TYPE_HIGIG2 | + +----+--------------------------------+ + | 25 | RTE_FLOW_ITEM_TYPE_RAW | + +----+--------------------------------+ + +.. note:: + + ``RTE_FLOW_ITEM_TYPE_GRE_KEY`` works only when checksum and routing + bits in the GRE header are equal to 0. + +Actions: + +.. _table_cnxk_supported_ingress_action_types: + +.. table:: Ingress action types + + +----+-----------------------------------------+ + | # | Action Type | + +====+=========================================+ + | 1 | RTE_FLOW_ACTION_TYPE_VOID | + +----+-----------------------------------------+ + | 2 | RTE_FLOW_ACTION_TYPE_MARK | + +----+-----------------------------------------+ + | 3 | RTE_FLOW_ACTION_TYPE_FLAG | + +----+-----------------------------------------+ + | 4 | RTE_FLOW_ACTION_TYPE_COUNT | + +----+-----------------------------------------+ + | 5 | RTE_FLOW_ACTION_TYPE_DROP | + +----+-----------------------------------------+ + | 6 | RTE_FLOW_ACTION_TYPE_QUEUE | + +----+-----------------------------------------+ + | 7 | RTE_FLOW_ACTION_TYPE_RSS | + +----+-----------------------------------------+ + | 8 | RTE_FLOW_ACTION_TYPE_PF | + +----+-----------------------------------------+ + | 9 | RTE_FLOW_ACTION_TYPE_VF | + +----+-----------------------------------------+ + | 10 | RTE_FLOW_ACTION_TYPE_OF_POP_VLAN | + +----+-----------------------------------------+ + +.. _table_cnxk_supported_egress_action_types: + +.. table:: Egress action types + + +----+-----------------------------------------+ + | # | Action Type | + +====+=========================================+ + | 1 | RTE_FLOW_ACTION_TYPE_COUNT | + +----+-----------------------------------------+ + | 2 | RTE_FLOW_ACTION_TYPE_DROP | + +----+-----------------------------------------+ + | 3 | RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN | + +----+-----------------------------------------+ + | 4 | RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID | + +----+-----------------------------------------+ + | 5 | RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP | + +----+-----------------------------------------+ + +Custom protocols supported in RTE Flow +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The ``RTE_FLOW_ITEM_TYPE_RAW`` can be used to parse the below custom protocols. + +* ``vlan_exdsa`` and ``exdsa`` can be parsed at L2 level. +* ``NGIO`` can be parsed at L3 level. + +For ``vlan_exdsa`` and ``exdsa``, the port has to be configured with the +respective switch header. + +For example:: + + -a 0002:02:00.0,switch_header="vlan_exdsa" + +The below fields of ``struct rte_flow_item_raw`` shall be used to specify the +pattern. + +- ``relative`` Selects the layer at which parsing is done. + + - 0 for ``exdsa`` and ``vlan_exdsa``. + + - 1 for ``NGIO``. + +- ``offset`` The offset in the header where the pattern should be matched. +- ``length`` Length of the pattern. +- ``pattern`` Pattern as a byte string. + +Example usage in testpmd:: + + ./dpdk-testpmd -c 3 -w 0002:02:00.0,switch_header=exdsa -- -i \ + --rx-offloads=0x00080000 --rxq 8 --txq 8 + testpmd> flow create 0 ingress pattern eth / raw relative is 0 pattern \ + spec ab pattern mask ab offset is 4 / end actions queue index 1 / end diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c index c76b6281c..36b437a18 100644 --- a/drivers/net/cnxk/cnxk_ethdev_devargs.c +++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c @@ -99,6 +99,13 @@ parse_switch_header_type(const char *key, const char *value, void *extra_args) if (strcmp(value, "chlen90b") == 0) *(uint16_t *)extra_args = ROC_PRIV_FLAGS_LEN_90B; + + if (strcmp(value, "exdsa") == 0) + *(uint16_t *)extra_args = ROC_PRIV_FLAGS_EXDSA; + + if (strcmp(value, "vlan_exdsa") == 0) + *(uint16_t *)extra_args = ROC_PRIV_FLAGS_VLAN_EXDSA; + return 0; } diff --git a/drivers/net/cnxk/cnxk_rte_flow.c b/drivers/net/cnxk/cnxk_rte_flow.c index 213125b56..32c1b5dee 100644 --- a/drivers/net/cnxk/cnxk_rte_flow.c +++ b/drivers/net/cnxk/cnxk_rte_flow.c @@ -15,8 +15,8 @@ const struct cnxk_rte_flow_term_info term[] = { [RTE_FLOW_ITEM_TYPE_IPV6] = {ROC_NPC_ITEM_TYPE_IPV6, sizeof(struct rte_flow_item_ipv6)}, [RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4] = { - ROC_NPC_ITEM_TYPE_ARP_ETH_IPV4, - sizeof(struct rte_flow_item_arp_eth_ipv4)}, + ROC_NPC_ITEM_TYPE_ARP_ETH_IPV4, + sizeof(struct rte_flow_item_arp_eth_ipv4)}, [RTE_FLOW_ITEM_TYPE_MPLS] = {ROC_NPC_ITEM_TYPE_MPLS, sizeof(struct rte_flow_item_mpls)}, [RTE_FLOW_ITEM_TYPE_ICMP] = {ROC_NPC_ITEM_TYPE_ICMP, @@ -50,10 +50,10 @@ const struct cnxk_rte_flow_term_info term[] = { [RTE_FLOW_ITEM_TYPE_ANY] = {ROC_NPC_ITEM_TYPE_ANY, 0}, [RTE_FLOW_ITEM_TYPE_GRE_KEY] = {ROC_NPC_ITEM_TYPE_GRE_KEY, sizeof(uint32_t)}, - [RTE_FLOW_ITEM_TYPE_HIGIG2] = { - ROC_NPC_ITEM_TYPE_HIGIG2, - sizeof(struct rte_flow_item_higig2_hdr)} -}; + [RTE_FLOW_ITEM_TYPE_HIGIG2] = {ROC_NPC_ITEM_TYPE_HIGIG2, + sizeof(struct rte_flow_item_higig2_hdr)}, + [RTE_FLOW_ITEM_TYPE_RAW] = {ROC_NPC_ITEM_TYPE_RAW, + sizeof(struct rte_flow_item_raw)}}; static int npc_rss_action_validate(struct rte_eth_dev *eth_dev,