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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT022.mail.protection.outlook.com (10.13.175.199) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4287.22 via Frontend Transport; Fri, 2 Jul 2021 06:18:36 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 2 Jul 2021 06:18:35 +0000 From: Suanming Mou To: , CC: , , Date: Fri, 2 Jul 2021 09:17:57 +0300 Message-ID: <20210702061816.10454-4-suanmingm@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20210702061816.10454-1-suanmingm@nvidia.com> References: <20210527093403.1153127-1-suanmingm@nvidia.com> <20210702061816.10454-1-suanmingm@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 12c04215-15ae-48d4-cc36-08d93d213a40 X-MS-TrafficTypeDiagnostic: DM6PR12MB2892: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:156; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2021 06:18:36.8446 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 12c04215-15ae-48d4-cc36-08d93d213a40 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2892 Subject: [dpdk-dev] [PATCH v3 03/22] net/mlx5: add index pool foreach define X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" In some cases, application may want to know all the allocated index in order to apply some operations to the allocated index. This commit adds the indexed pool functions to support foreach operation. Signed-off-by: Suanming Mou Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_utils.c | 86 +++++++++++++++++++++++++++++++++++ drivers/net/mlx5/mlx5_utils.h | 8 ++++ 2 files changed, 94 insertions(+) diff --git a/drivers/net/mlx5/mlx5_utils.c b/drivers/net/mlx5/mlx5_utils.c index 215024632d..0ed279e162 100644 --- a/drivers/net/mlx5/mlx5_utils.c +++ b/drivers/net/mlx5/mlx5_utils.c @@ -839,6 +839,92 @@ mlx5_ipool_destroy(struct mlx5_indexed_pool *pool) return 0; } +void +mlx5_ipool_flush_cache(struct mlx5_indexed_pool *pool) +{ + uint32_t i, j; + struct mlx5_indexed_cache *gc; + struct rte_bitmap *ibmp; + uint32_t bmp_num, mem_size; + + if (!pool->cfg.per_core_cache) + return; + gc = pool->gc; + if (!gc) + return; + /* Reset bmp. */ + bmp_num = mlx5_trunk_idx_offset_get(pool, gc->n_trunk_valid); + mem_size = rte_bitmap_get_memory_footprint(bmp_num); + pool->bmp_mem = pool->cfg.malloc(MLX5_MEM_ZERO, mem_size, + RTE_CACHE_LINE_SIZE, rte_socket_id()); + if (!pool->bmp_mem) { + DRV_LOG(ERR, "Ipool bitmap mem allocate failed.\n"); + return; + } + ibmp = rte_bitmap_init_with_all_set(bmp_num, pool->bmp_mem, mem_size); + if (!ibmp) { + pool->cfg.free(pool->bmp_mem); + pool->bmp_mem = NULL; + DRV_LOG(ERR, "Ipool bitmap create failed.\n"); + return; + } + pool->ibmp = ibmp; + /* Clear global cache. */ + for (i = 0; i < gc->len; i++) + rte_bitmap_clear(ibmp, gc->idx[i] - 1); + /* Clear core cache. */ + for (i = 0; i < RTE_MAX_LCORE; i++) { + struct mlx5_ipool_per_lcore *ilc = pool->cache[i]; + + if (!ilc) + continue; + for (j = 0; j < ilc->len; j++) + rte_bitmap_clear(ibmp, ilc->idx[j] - 1); + } +} + +static void * +mlx5_ipool_get_next_cache(struct mlx5_indexed_pool *pool, uint32_t *pos) +{ + struct rte_bitmap *ibmp; + uint64_t slab = 0; + uint32_t iidx = *pos; + + ibmp = pool->ibmp; + if (!ibmp || !rte_bitmap_scan(ibmp, &iidx, &slab)) { + if (pool->bmp_mem) { + pool->cfg.free(pool->bmp_mem); + pool->bmp_mem = NULL; + pool->ibmp = NULL; + } + return NULL; + } + iidx += __builtin_ctzll(slab); + rte_bitmap_clear(ibmp, iidx); + iidx++; + *pos = iidx; + return mlx5_ipool_get_cache(pool, iidx); +} + +void * +mlx5_ipool_get_next(struct mlx5_indexed_pool *pool, uint32_t *pos) +{ + uint32_t idx = *pos; + void *entry; + + if (pool->cfg.per_core_cache) + return mlx5_ipool_get_next_cache(pool, pos); + while (idx <= mlx5_trunk_idx_offset_get(pool, pool->n_trunk)) { + entry = mlx5_ipool_get(pool, idx); + if (entry) { + *pos = idx; + return entry; + } + idx++; + } + return NULL; +} + void mlx5_ipool_dump(struct mlx5_indexed_pool *pool) { diff --git a/drivers/net/mlx5/mlx5_utils.h b/drivers/net/mlx5/mlx5_utils.h index 0469062695..737dd7052d 100644 --- a/drivers/net/mlx5/mlx5_utils.h +++ b/drivers/net/mlx5/mlx5_utils.h @@ -261,6 +261,9 @@ struct mlx5_indexed_pool { /* Global cache. */ struct mlx5_ipool_per_lcore *cache[RTE_MAX_LCORE]; /* Local cache. */ + struct rte_bitmap *ibmp; + void *bmp_mem; + /* Allocate objects bitmap. Use during flush. */ }; }; #ifdef POOL_DEBUG @@ -862,4 +865,9 @@ struct { \ (entry); \ idx++, (entry) = mlx5_l3t_get_next((tbl), &idx)) +#define MLX5_IPOOL_FOREACH(ipool, idx, entry) \ + for ((idx) = 0, mlx5_ipool_flush_cache((ipool)), \ + (entry) = mlx5_ipool_get_next((ipool), &idx); \ + (entry); idx++, (entry) = mlx5_ipool_get_next((ipool), &idx)) + #endif /* RTE_PMD_MLX5_UTILS_H_ */