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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT054.mail.protection.outlook.com (10.13.174.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4287.22 via Frontend Transport; Fri, 2 Jul 2021 06:18:34 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 2 Jul 2021 06:18:31 +0000 From: Suanming Mou To: , CC: , , Date: Fri, 2 Jul 2021 09:17:55 +0300 Message-ID: <20210702061816.10454-2-suanmingm@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20210702061816.10454-1-suanmingm@nvidia.com> References: <20210527093403.1153127-1-suanmingm@nvidia.com> <20210702061816.10454-1-suanmingm@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 491a74a0-7766-45ea-1f5c-08d93d213893 X-MS-TrafficTypeDiagnostic: BL1PR12MB5064: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6430; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2021 06:18:34.0557 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 491a74a0-7766-45ea-1f5c-08d93d213893 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5064 Subject: [dpdk-dev] [PATCH v3 01/22] net/mlx5: allow limiting the index pool maximum index X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Some ipool instances in the driver are used as ID\index allocator and added other logic in order to work with limited index values. Add a new configuration for ipool specify the maximum index value. The ipool will ensure that no index bigger than the maximum value is provided. Use this configuration in ID allocator cases instead of the current logics. This patch add the maximum ID configurable for the index pool. Signed-off-by: Suanming Mou Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5_utils.c | 14 ++++++++++++-- drivers/net/mlx5/mlx5_utils.h | 1 + 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/mlx5_utils.c b/drivers/net/mlx5/mlx5_utils.c index 18fe23e4fb..bf2b2ebc72 100644 --- a/drivers/net/mlx5/mlx5_utils.c +++ b/drivers/net/mlx5/mlx5_utils.c @@ -270,6 +270,9 @@ mlx5_ipool_create(struct mlx5_indexed_pool_config *cfg) if (i > 0) pool->grow_tbl[i] += pool->grow_tbl[i - 1]; } + if (!pool->cfg.max_idx) + pool->cfg.max_idx = + mlx5_trunk_idx_offset_get(pool, TRUNK_MAX_IDX + 1); return pool; } @@ -282,9 +285,11 @@ mlx5_ipool_grow(struct mlx5_indexed_pool *pool) size_t trunk_size = 0; size_t data_size; size_t bmp_size; - uint32_t idx; + uint32_t idx, cur_max_idx, i; - if (pool->n_trunk_valid == TRUNK_MAX_IDX) + cur_max_idx = mlx5_trunk_idx_offset_get(pool, pool->n_trunk_valid); + if (pool->n_trunk_valid == TRUNK_MAX_IDX || + cur_max_idx >= pool->cfg.max_idx) return -ENOMEM; if (pool->n_trunk_valid == pool->n_trunk) { /* No free trunk flags, expand trunk list. */ @@ -336,6 +341,11 @@ mlx5_ipool_grow(struct mlx5_indexed_pool *pool) trunk->bmp = rte_bitmap_init_with_all_set(data_size, &trunk->data [RTE_CACHE_LINE_ROUNDUP(data_size * pool->cfg.size)], bmp_size); + /* Clear the overhead bits in the trunk if it happens. */ + if (cur_max_idx + data_size > pool->cfg.max_idx) { + for (i = pool->cfg.max_idx - cur_max_idx; i < data_size; i++) + rte_bitmap_clear(trunk->bmp, i); + } MLX5_ASSERT(trunk->bmp); pool->n_trunk_valid++; #ifdef POOL_DEBUG diff --git a/drivers/net/mlx5/mlx5_utils.h b/drivers/net/mlx5/mlx5_utils.h index b54517c6df..15870e14c2 100644 --- a/drivers/net/mlx5/mlx5_utils.h +++ b/drivers/net/mlx5/mlx5_utils.h @@ -208,6 +208,7 @@ struct mlx5_indexed_pool_config { uint32_t need_lock:1; /* Lock is needed for multiple thread usage. */ uint32_t release_mem_en:1; /* Rlease trunk when it is free. */ + uint32_t max_idx; /* The maximum index can be allocated. */ const char *type; /* Memory allocate type name. */ void *(*malloc)(uint32_t flags, size_t size, unsigned int align, int socket);