[v3,00/22] net/mlx5: insertion rate optimization
Message ID | 20210702061816.10454-1-suanmingm@nvidia.com (mailing list archive) |
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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT054.mail.protection.outlook.com (10.13.174.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4287.22 via Frontend Transport; Fri, 2 Jul 2021 06:18:33 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 2 Jul 2021 06:18:30 +0000 From: Suanming Mou <suanmingm@nvidia.com> To: <viacheslavo@nvidia.com>, <matan@nvidia.com> CC: <rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org> Date: Fri, 2 Jul 2021 09:17:54 +0300 Message-ID: <20210702061816.10454-1-suanmingm@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20210527093403.1153127-1-suanmingm@nvidia.com> References: <20210527093403.1153127-1-suanmingm@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a78df45f-fb4a-48a1-5ece-08d93d213831 X-MS-TrafficTypeDiagnostic: DM6PR12MB3289: X-Microsoft-Antispam-PRVS: <DM6PR12MB328934373FCA671F1D3A2017C11F9@DM6PR12MB3289.namprd12.prod.outlook.com> X-MS-Oob-TLC-OOBClassifiers: OLM:8882; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2021 06:18:33.4431 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a78df45f-fb4a-48a1-5ece-08d93d213831 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3289 Subject: [dpdk-dev] [PATCH v3 00/22] net/mlx5: insertion rate optimization X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> |
Message
Suanming Mou
July 2, 2021, 6:17 a.m. UTC
This patch series optimize the flow insertion rate with adding local cache to index pool and list. For object which wants efficient index allocate and free, local cache will be very helpful. For index pool, two level cache is added, one as local and another as global. The global cache is able to save all the allocated index. That means all the allocated index will not be freed. Once the local cache is full, the extra index will be flushed to the global cache. Once local cache is empty, first try to fetch more index from global, if global is still empty, allocate new trunk and more index. For list, sub local core list is introduced. The allocated objects will be added and released only from local list without any locks. Only the objects need to be shared will be synced from global list. --- v3: fix Windows compilation issue v2: add the list per-lcore cache optimization --- Matan Azrad (9): net/mlx5: optimize modify header action memory net/mlx5: remove cache term from the list utility net/mlx5: add per lcore cache to the list utility net/mlx5: minimize list critical sections net/mlx5: manage list cache entries release net/mlx5: relax the list utility atomic operations net/mlx5: allocate list memory by the create API common/mlx5: add per-lcore cache to hash list utility net/mlx5: move modify header allocator to ipool Suanming Mou (13): net/mlx5: allow limiting the index pool maximum index net/mlx5: add indexed pool local cache net/mlx5: add index pool foreach define net/mlx5: replace flow list with index pool net/mlx5: adjust the hash bucket size common/mlx5: allocate cache list memory individually net/mlx5: enable index pool per-core cache net/mlx5: optimize hash list table allocate on demand common/mlx5: optimize cache list object memory net/mlx5: change memory release configuration net/mlx5: support index pool none local core operations net/mlx5: support list none local core operations net/mlx5: optimize Rx queue match doc/guides/nics/mlx5.rst | 5 + doc/guides/rel_notes/release_21_08.rst | 6 + drivers/common/mlx5/linux/mlx5_glue.h | 1 + drivers/common/mlx5/mlx5_common.h | 2 + drivers/common/mlx5/mlx5_common_utils.c | 569 ++++++++--- drivers/common/mlx5/mlx5_common_utils.h | 289 ++++-- drivers/common/mlx5/version.map | 7 + drivers/net/mlx5/linux/mlx5_flow_os.h | 3 +- drivers/net/mlx5/linux/mlx5_os.c | 209 ++-- drivers/net/mlx5/mlx5.c | 34 +- drivers/net/mlx5/mlx5.h | 46 +- drivers/net/mlx5/mlx5_defs.h | 12 +- drivers/net/mlx5/mlx5_flow.c | 305 +++--- drivers/net/mlx5/mlx5_flow.h | 210 ++-- drivers/net/mlx5/mlx5_flow_dv.c | 1203 +++++++++++++++-------- drivers/net/mlx5/mlx5_rx.h | 14 +- drivers/net/mlx5/mlx5_rxq.c | 136 ++- drivers/net/mlx5/mlx5_trigger.c | 8 +- drivers/net/mlx5/mlx5_utils.c | 617 ++++++++---- drivers/net/mlx5/mlx5_utils.h | 255 ++--- drivers/net/mlx5/windows/mlx5_os.c | 11 +- 21 files changed, 2531 insertions(+), 1411 deletions(-)