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marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT042.mail.protection.outlook.com (10.13.177.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4287.22 via Frontend Transport; Thu, 1 Jul 2021 13:27:13 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 1 Jul 2021 13:27:02 +0000 From: Shiri Kuzin To: CC: , , Date: Thu, 1 Jul 2021 16:26:02 +0300 Message-ID: <20210701132609.53727-9-shirik@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210701132609.53727-1-shirik@nvidia.com> References: <20210509160507.224644-1-matan@nvidia.com> <20210701132609.53727-1-shirik@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 45262b9d-0623-4c5f-b707-08d93c93f01a X-MS-TrafficTypeDiagnostic: DM8PR12MB5416: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:117; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jul 2021 13:27:13.4048 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 45262b9d-0623-4c5f-b707-08d93c93f01a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT042.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5416 Subject: [dpdk-dev] [PATCH v5 08/15] crypto/mlx5: create login object using DevX X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" To work with crypto engines that are marked with wrapped_import_method, a login session is required. A crypto login object needs to be created using DevX. The crypto login object contains: - The credential pointer. - The import_KEK pointer to be used for all secured information communicated in crypto commands (key fields), including the provided credential in this command. - The credential secret, wrapped by the import_KEK indicated in this command. Size includes 8 bytes IV for wrapping. Added devargs for the required login values: - wcs_file - path to the file containing the credential. - import_kek_id - the import KEK pointer. - credential_id - the credential pointer. Create the login DevX object in pci_probe function and destroy it in pci_remove. Destroying the crypto login object means logout. Signed-off-by: Shiri Kuzin Acked-by: Matan Azrad --- doc/guides/cryptodevs/mlx5.rst | 60 +++++++++++++++++ drivers/crypto/mlx5/mlx5_crypto.c | 103 ++++++++++++++++++++++++++++++ drivers/crypto/mlx5/mlx5_crypto.h | 7 ++ 3 files changed, 170 insertions(+) diff --git a/doc/guides/cryptodevs/mlx5.rst b/doc/guides/cryptodevs/mlx5.rst index ece881220e..6cae5affbd 100644 --- a/doc/guides/cryptodevs/mlx5.rst +++ b/doc/guides/cryptodevs/mlx5.rst @@ -44,6 +44,51 @@ To get the best performances: Enabling librte_crypto_mlx5 causes DPDK applications to be linked against libibverbs. +In order to move the device to crypto operational mode, credential and KEK +(Key Encrypting Key) should be set as the first step. +The credential will be used by the software in order to perform crypto login, and the KEK is +the AES Key Wrap Algorithm (rfc3394) key that will be used for sensitive data +wrapping. +The credential and the AES-XTS keys should be provided to the hardware, as ciphertext +encrypted by the KEK. + +When crypto engines are defined to work in wrapped import method, they come out +of the factory in Commissioning mode, and thus, cannot be used for crypto operations +yet. A dedicated tool is used for changing the mode from Commissioning to +Operational, while setting the first import_KEK and credential in plaintext. +The mlxreg dedicated tool should be used as follows: + +- Set CRYPTO_OPERATIONAL register to set the device in crypto operational mode. + + The input to this tool is: + The first credential in plaintext, 40B. + The first import_KEK in plaintext: kek size 0 for 16B or 1 for 32B, kek data. + + Example: + mlxreg -d /dev/mst/mt4123_pciconf0 --reg_name CRYPTO_OPERATIONAL --get + + The "wrapped_crypto_operational" value will be "0x00000000". + The command to set the register should be executed only once, and all the + values mentioned above should be specified in the same command. + + Example: + mlxreg -d /dev/mst/mt4123_pciconf0 --reg_name CRYPTO_OPERATIONAL + --set "credential[0]=0x10000000, credential[1]=0x10000000, kek[0]=0x00000000" + + All values not specified will remain 0. + "wrapped_crypto_going_to_commissioning" and "wrapped_crypto_operational" + should not be specified. + + All the device ports should set it in order to move to operational mode. + +- Query CRYPTO_OPERATIONAL register to make sure the device is in Operational + mode. + + Example: + mlxreg -d /dev/mst/mt4123_pciconf0 --reg_name CRYPTO_OPERATIONAL --get + The "wrapped_crypto_operational" value will be "0x00000001" if the mode was + successfully changed to operational mode. + Driver options -------------- @@ -53,6 +98,21 @@ Driver options Select the class of the driver that should probe the device. `crypto` for the mlx5 crypto driver. +- ``wcs_file`` parameter [string] - mandatory + + File path including only the wrapped credential in string format of hexadecimal + numbers, represent 48 bytes (8 bytes IV added by the AES key wrap algorithm). + +- ``import_kek_id`` parameter [int] + + The identifier of the KEK, default value is 0 represents the operational + register import_kek.. + +- ``credential_id`` parameter [int] + + The identifier of the credential, default value is 0 represents the operational + register credential. + Supported NICs -------------- diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index 367a4759b3..95bbb83fc3 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -457,6 +457,101 @@ mlx5_crypto_hw_global_prepare(struct mlx5_crypto_priv *priv) return 0; } + +static int +mlx5_crypto_args_check_handler(const char *key, const char *val, void *opaque) +{ + struct mlx5_crypto_devarg_params *devarg_prms = opaque; + struct mlx5_devx_crypto_login_attr *attr = &devarg_prms->login_attr; + unsigned long tmp; + FILE *file; + int ret; + int i; + + if (strcmp(key, "class") == 0) + return 0; + if (strcmp(key, "wcs_file") == 0) { + file = fopen(val, "rb"); + if (file == NULL) { + rte_errno = ENOTSUP; + return -rte_errno; + } + for (i = 0 ; i < MLX5_CRYPTO_CREDENTIAL_SIZE ; i++) { + ret = fscanf(file, "%02hhX", &attr->credential[i]); + if (ret <= 0) { + fclose(file); + DRV_LOG(ERR, + "Failed to read credential from file."); + rte_errno = EINVAL; + return -rte_errno; + } + } + fclose(file); + devarg_prms->login_devarg = true; + return 0; + } + errno = 0; + tmp = strtoul(val, NULL, 0); + if (errno) { + DRV_LOG(WARNING, "%s: \"%s\" is an invalid integer.", key, val); + return -errno; + } + if (strcmp(key, "import_kek_id") == 0) + attr->session_import_kek_ptr = (uint32_t)tmp; + else if (strcmp(key, "credential_id") == 0) + attr->credential_pointer = (uint32_t)tmp; + else + DRV_LOG(WARNING, "Invalid key %s.", key); + return 0; +} + +static struct mlx5_devx_obj * +mlx5_crypto_config_login(struct rte_devargs *devargs, + struct ibv_context *ctx) +{ + /* + * Set credential pointer and session import KEK pointer to a default + * value of 0. + */ + struct mlx5_crypto_devarg_params login = { + .login_devarg = false, + .login_attr = { + .credential_pointer = 0, + .session_import_kek_ptr = 0, + } + }; + struct rte_kvargs *kvlist; + + if (devargs == NULL) { + DRV_LOG(ERR, + "No login devargs in order to enable crypto operations in the device."); + rte_errno = EINVAL; + return NULL; + } + kvlist = rte_kvargs_parse(devargs->args, NULL); + if (kvlist == NULL) { + DRV_LOG(ERR, "Failed to parse devargs."); + rte_errno = EINVAL; + return NULL; + } + if (rte_kvargs_process(kvlist, NULL, mlx5_crypto_args_check_handler, + &login) != 0) { + DRV_LOG(ERR, "Devargs handler function Failed."); + rte_kvargs_free(kvlist); + rte_errno = EINVAL; + return NULL; + } + rte_kvargs_free(kvlist); + if (login.login_devarg == false) { + DRV_LOG(ERR, + "No login credential devarg in order to enable crypto operations " + "in the device."); + rte_errno = EINVAL; + return NULL; + } + return mlx5_devx_cmd_create_crypto_login_obj(ctx, &login.login_attr); +} + /** * Callback for memory event. * @@ -512,6 +607,7 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv, struct ibv_device *ibv; struct rte_cryptodev *crypto_dev; struct ibv_context *ctx; + struct mlx5_devx_obj *login; struct mlx5_crypto_priv *priv; struct mlx5_hca_attr attr = { 0 }; struct rte_cryptodev_pmd_init_params init_params = { @@ -550,6 +646,11 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv, rte_errno = ENOTSUP; return -ENOTSUP; } + login = mlx5_crypto_config_login(pci_dev->device.devargs, ctx); + if (login == NULL) { + DRV_LOG(ERR, "Failed to configure login."); + return -rte_errno; + } crypto_dev = rte_cryptodev_pmd_create(ibv->name, &pci_dev->device, &init_params); if (crypto_dev == NULL) { @@ -566,6 +667,7 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv, crypto_dev->driver_id = mlx5_crypto_driver_id; priv = crypto_dev->data->dev_private; priv->ctx = ctx; + priv->login_obj = login; priv->pci_dev = pci_dev; priv->crypto_dev = crypto_dev; if (mlx5_crypto_hw_global_prepare(priv) != 0) { @@ -614,6 +716,7 @@ mlx5_crypto_pci_remove(struct rte_pci_device *pdev) mlx5_mr_release_cache(&priv->mr_scache); mlx5_crypto_hw_global_release(priv); rte_cryptodev_pmd_destroy(priv->crypto_dev); + claim_zero(mlx5_devx_cmd_destroy(priv->login_obj)); claim_zero(mlx5_glue->close_device(priv->ctx)); } return 0; diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index d1ea8024d4..a45a210e58 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -29,6 +29,7 @@ struct mlx5_crypto_priv { struct mlx5_hlist *dek_hlist; /* Dek hash list. */ struct rte_cryptodev_config dev_config; struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ + struct mlx5_devx_obj *login_obj; }; struct mlx5_crypto_qp { @@ -48,6 +49,12 @@ struct mlx5_crypto_dek { bool size_is_48; /* Whether the key\data size is 48 bytes or not. */ } __rte_cache_aligned; + +struct mlx5_crypto_devarg_params { + bool login_devarg; + struct mlx5_devx_crypto_login_attr login_attr; +}; + int mlx5_crypto_dek_destroy(struct mlx5_crypto_priv *priv, struct mlx5_crypto_dek *dek);