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marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT042.mail.protection.outlook.com (10.13.177.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4287.22 via Frontend Transport; Thu, 1 Jul 2021 13:27:11 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 1 Jul 2021 13:26:56 +0000 From: Shiri Kuzin To: CC: , , Date: Thu, 1 Jul 2021 16:25:58 +0300 Message-ID: <20210701132609.53727-5-shirik@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210701132609.53727-1-shirik@nvidia.com> References: <20210509160507.224644-1-matan@nvidia.com> <20210701132609.53727-1-shirik@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7d7d73e4-8ba7-44ad-6419-08d93c93eee2 X-MS-TrafficTypeDiagnostic: DM8PR12MB5416: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2150; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jul 2021 13:27:11.3470 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7d7d73e4-8ba7-44ad-6419-08d93c93eee2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT042.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5416 Subject: [dpdk-dev] [PATCH v5 04/15] crypto/mlx5: add basic operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The basic dev control operations are configure, close and get info. Extended the existing support of configure and close: -mlx5_crypto_dev_configure- function used to configure device. -mlx5_crypto_dev_close- function used to close a configured device. Added config struct to user private data with the fields socket id, number of queue pairs and feature flags to be disabled. Signed-off-by: Shiri Kuzin Acked-by: Matan Azrad --- drivers/crypto/mlx5/mlx5_crypto.c | 26 +++++++++++++++++++------- drivers/crypto/mlx5/mlx5_crypto.h | 1 + 2 files changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index dd9685dcad..0ce46ffd2f 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -105,22 +105,27 @@ mlx5_crypto_dev_infos_get(struct rte_cryptodev *dev, } } -static unsigned int -mlx5_crypto_sym_session_get_size(struct rte_cryptodev *dev __rte_unused) -{ - return sizeof(struct mlx5_crypto_session); -} - static int mlx5_crypto_dev_configure(struct rte_cryptodev *dev, - struct rte_cryptodev_config *config __rte_unused) + struct rte_cryptodev_config *config) { struct mlx5_crypto_priv *priv = dev->data->dev_private; + if (config == NULL) { + DRV_LOG(ERR, "Invalid crypto dev configure parameters."); + return -EINVAL; + } + if ((config->ff_disable & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) != 0) { + DRV_LOG(ERR, + "Disabled symmetric crypto feature is not supported."); + return -ENOTSUP; + } if (mlx5_crypto_dek_setup(priv) != 0) { DRV_LOG(ERR, "Dek hash list creation has failed."); return -ENOMEM; } + priv->dev_config = *config; + DRV_LOG(DEBUG, "Device %u was configured.", dev->driver_id); return 0; } @@ -130,9 +135,16 @@ mlx5_crypto_dev_close(struct rte_cryptodev *dev) struct mlx5_crypto_priv *priv = dev->data->dev_private; mlx5_crypto_dek_unset(priv); + DRV_LOG(DEBUG, "Device %u was closed.", dev->driver_id); return 0; } +static unsigned int +mlx5_crypto_sym_session_get_size(struct rte_cryptodev *dev __rte_unused) +{ + return sizeof(struct mlx5_crypto_session); +} + static int mlx5_crypto_sym_session_configure(struct rte_cryptodev *dev, struct rte_crypto_sym_xform *xform, diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index 5a54cb0dca..4c07356028 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -24,6 +24,7 @@ struct mlx5_crypto_priv { uint32_t pdn; /* Protection Domain number. */ struct ibv_pd *pd; struct mlx5_hlist *dek_hlist; /* Dek hash list. */ + struct rte_cryptodev_config dev_config; }; struct mlx5_crypto_dek {