From patchwork Thu Jul 1 07:00:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: danat@marvell.com X-Patchwork-Id: 95101 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 27259A0A0C; Thu, 1 Jul 2021 09:00:14 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1258B4067C; Thu, 1 Jul 2021 09:00:14 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id D794140141 for ; Thu, 1 Jul 2021 09:00:11 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1616tD7i016761 for ; Thu, 1 Jul 2021 00:00:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0220; bh=XKPF2UiGPp861a3s7KbXfcnokKZ/F9gOq8dPn2f6dik=; b=S47F/pRenNfap5O5aRffmeiCcWoDERV/xHbwt3fABCv0dVMPhIVkZkG40AiFAda1sTKG Kprv5isQzmwEofag//TP3ggtKy0G9sStBa/Q0hI3JrwWUNoxrwC43TTM0YNUVQc9ifkk CYZS3DUY9PYpxL7RX4kACF1lgk3YUP4ofc3BOSt8gQxrbbUPgWzlpItVm/U/bEidcuFx bm2L/WkOLCe6XetW1ThM2L7zrjv1Wkt203lwOZ7By4UVbcz9QT2LXYAPdsBhRwfAmpEl iq7M+HjR7aUJkkLnlz3S7wyCO+vxFIR7AX8dTj9Mj2tIKD0PjUcyOIbgWJIy1NwY8V/F 1w== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 39gxj0j83x-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 01 Jul 2021 00:00:11 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 1 Jul 2021 00:00:09 -0700 Received: from jupiter077.il.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 1 Jul 2021 00:00:07 -0700 From: To: CC: , , , Date: Thu, 1 Jul 2021 10:00:05 +0300 Message-ID: <20210701070005.31140-1-danat@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Proofpoint-GUID: rK21X-v8WgIBRK4R3cSBu0l4b5zBezfa X-Proofpoint-ORIG-GUID: rK21X-v8WgIBRK4R3cSBu0l4b5zBezfa X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-01_01:2021-06-30, 2021-07-01 signatures=0 Subject: [dpdk-dev] [PATCH] crypto/mvsam: add comments for three crypto devs X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Michael Shamis Till now comments explain queue mapping per one and two crypto devices. Now added comments for queue mapping for three crypto devices supported in CN9132. Signed-off-by: Michael Shamis Reviewed-by: Liron Himi --- drivers/crypto/mvsam/rte_mrvl_pmd_ops.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/mvsam/rte_mrvl_pmd_ops.c b/drivers/crypto/mvsam/rte_mrvl_pmd_ops.c index 1a0a9fc14..75bb8adb8 100644 --- a/drivers/crypto/mvsam/rte_mrvl_pmd_ops.c +++ b/drivers/crypto/mvsam/rte_mrvl_pmd_ops.c @@ -663,6 +663,11 @@ mrvl_crypto_pmd_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id, } /* + * In case just one engine is enabled mapping will look as + * follows: + * qp: 0 1 2 3 + * cio-x:y: cio-0:0, cio-0:1, cio-0:2, cio-0:3 + * * In case two crypto engines are enabled qps will * be evenly spread among them. Even and odd qps will * be handled by cio-0 and cio-1 respectively. qp-cio mapping @@ -674,10 +679,17 @@ mrvl_crypto_pmd_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id, * qp: 4 5 6 7 * cio-x:y: cio-0:2, cio-1:2, cio-0:3, cio-1:3 * - * In case just one engine is enabled mapping will look as - * follows: + * In case of three crypto engines are enabled qps will + * be mapped as following: + * * qp: 0 1 2 3 - * cio-x:y: cio-0:0, cio-0:1, cio-0:2, cio-0:3 + * cio-x:y: cio-0:0, cio-1:0, cio-2:0, cio-0:1 + * + * qp: 4 5 6 7 + * cio-x:y: cio-1:1, cio-2:1, cio-0:2, cio-1:2 + * + * qp: 8 9 10 11 + * cio-x:y: cio-2:2, cio-0:3, cio-1:3, cio-2:3 */ n = snprintf(match, sizeof(match), "cio-%u:%u", qp_id % num, qp_id / num);