diff mbox series

[v2,09/16] crypto/qat: add chacha-poly in ucs spc mode

Message ID 20210628163434.77741-10-arkadiuszx.kusztal@intel.com (mailing list archive)
State Accepted, archived
Delegated to: akhil goyal
Headers show
Series Add support for fourth generation of Intel QuickAssist Technology devices | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Kusztal, ArkadiuszX June 28, 2021, 4:34 p.m. UTC
This commit adds Chacha20-Poly1305 aglorithm that works
in UCS (Unified crypto slice) SPC(Single-Pass) mode.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
 drivers/crypto/qat/qat_sym_capabilities.h | 32 ++++++++++++++++++++++-
 drivers/crypto/qat/qat_sym_session.c      |  2 ++
 2 files changed, 33 insertions(+), 1 deletion(-)

Comments

Zhang, Roy Fan June 29, 2021, 12:20 p.m. UTC | #1
> -----Original Message-----
> From: Kusztal, ArkadiuszX <arkadiuszx.kusztal@intel.com>
> Sent: Monday, June 28, 2021 5:34 PM
> To: dev@dpdk.org
> Cc: gakhil@marvell.com; Trahe, Fiona <fiona.trahe@intel.com>; Zhang, Roy
> Fan <roy.fan.zhang@intel.com>; Kusztal, ArkadiuszX
> <arkadiuszx.kusztal@intel.com>
> Subject: [PATCH v2 09/16] crypto/qat: add chacha-poly in ucs spc mode
> 
> This commit adds Chacha20-Poly1305 aglorithm that works
> in UCS (Unified crypto slice) SPC(Single-Pass) mode.
> 
> Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>

Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
diff mbox series

Patch

diff --git a/drivers/crypto/qat/qat_sym_capabilities.h b/drivers/crypto/qat/qat_sym_capabilities.h
index fc8e667687..5c6e723466 100644
--- a/drivers/crypto/qat/qat_sym_capabilities.h
+++ b/drivers/crypto/qat/qat_sym_capabilities.h
@@ -1144,7 +1144,37 @@ 
 				},					\
 			}, }						\
 		}, }							\
-	}								\
+	},								\
+	{	/* Chacha20-Poly1305 */					\
+	.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,			\
+		{.sym = {						\
+			.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,	\
+			{.aead = {					\
+				.algo = RTE_CRYPTO_AEAD_CHACHA20_POLY1305, \
+				.block_size = 64,			\
+				.key_size = {				\
+					.min = 32,			\
+					.max = 32,			\
+					.increment = 0			\
+				},					\
+				.digest_size = {			\
+					.min = 16,			\
+					.max = 16,			\
+					.increment = 0			\
+				},					\
+				.aad_size = {				\
+					.min = 0,			\
+					.max = 240,			\
+					.increment = 1			\
+				},					\
+				.iv_size = {				\
+					.min = 12,			\
+					.max = 12,			\
+					.increment = 0			\
+				},					\
+			}, }						\
+		}, }							\
+	}
 
 
 
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index 019c9f4f02..a49da8e364 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -922,6 +922,8 @@  qat_sym_session_configure_aead(struct rte_cryptodev *dev,
 	case RTE_CRYPTO_AEAD_CHACHA20_POLY1305:
 		if (aead_xform->key.length != ICP_QAT_HW_CHACHAPOLY_KEY_SZ)
 			return -EINVAL;
+		if (qat_dev_gen == QAT_GEN4)
+			session->is_ucs = 1;
 		session->qat_cipher_alg =
 				ICP_QAT_HW_CIPHER_ALGO_CHACHA20_POLY1305;
 		qat_sym_session_handle_single_pass(session,