From patchwork Mon Jun 21 06:37:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Zhang X-Patchwork-Id: 94584 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7B950A0547; Mon, 21 Jun 2021 08:47:21 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 753CA41180; Mon, 21 Jun 2021 08:47:00 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id DB3104119B for ; Mon, 21 Jun 2021 08:46:58 +0200 (CEST) IronPort-SDR: jNpcNXDeWxdGhxH01rD1R5zXKFlcnhri7LAeezgJ2XQs3tTzIibhgXxZ8ErNPybZ4d2v0N8P6n OZgLpGq+hDHA== X-IronPort-AV: E=McAfee;i="6200,9189,10021"; a="270633619" X-IronPort-AV: E=Sophos;i="5.83,289,1616482800"; d="scan'208";a="270633619" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2021 23:46:58 -0700 IronPort-SDR: 0OBBBvRRGAzbxHzY1/IcrmOUre+hc9QQZst8Q/Tw4l9E1RBaPdDw619xfbRHQbgRbGzXUYZ5KT 0JAPQiYIa7Nw== X-IronPort-AV: E=Sophos;i="5.83,289,1616482800"; d="scan'208";a="486380478" Received: from unknown (HELO intel-npg-odc-srv03.cd.intel.com) ([10.240.178.145]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Jun 2021 23:46:55 -0700 From: Robin Zhang To: dev@dpdk.org Cc: beilei.xing@intel.com, junfeng.guo@intel.com, stevex.yang@intel.com, Robin Zhang , Przemyslaw Patynowski Date: Mon, 21 Jun 2021 06:37:04 +0000 Message-Id: <20210621063708.4014937-11-robinx.zhang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210621063708.4014937-1-robinx.zhang@intel.com> References: <20210618063851.3694702-1-robinx.zhang@intel.com> <20210621063708.4014937-1-robinx.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 10/14] net/i40e/base: add flags and fields for double vlan processing X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add flags for outer vlan and include set port parameters in Linux compilation. Add flags, which describe port and switch state for both double vlan functionality and outer vlan processing. Signed-off-by: Przemyslaw Patynowski Signed-off-by: Robin Zhang --- drivers/net/i40e/base/i40e_adminq_cmd.h | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h index 1aafe1de38..646cfd0398 100644 --- a/drivers/net/i40e/base/i40e_adminq_cmd.h +++ b/drivers/net/i40e/base/i40e_adminq_cmd.h @@ -768,6 +768,7 @@ struct i40e_aqc_set_switch_config { #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004 +#define I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN 0x0008 __le16 valid_flags; /* The ethertype in switch_tag is dropped on ingress and used * internally by the switch. Set this to zero for the default @@ -904,7 +905,7 @@ struct i40e_aqc_vsi_properties_data { u8 sec_reserved; /* VLAN section */ __le16 pvid; /* VLANS include priority bits */ - __le16 fcoe_pvid; + __le16 outer_vlan; u8 port_vlan_flags; #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ @@ -920,7 +921,24 @@ struct i40e_aqc_vsi_properties_data { #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 - u8 pvlan_reserved[3]; + u8 outer_vlan_flags; +#define I40E_AQ_VSI_OVLAN_MODE_SHIFT 0x00 +#define I40E_AQ_VSI_OVLAN_MODE_MASK (0x03 << \ + I40E_AQ_VSI_OVLAN_MODE_SHIFT) +#define I40E_AQ_VSI_OVLAN_MODE_UNTAGGED 0x01 +#define I40E_AQ_VSI_OVLAN_MODE_TAGGED 0x02 +#define I40E_AQ_VSI_OVLAN_MODE_ALL 0x03 +#define I40E_AQ_VSI_OVLAN_INSERT_PVID 0x04 +#define I40E_AQ_VSI_OVLAN_EMOD_SHIFT 0x03 +#define I40E_AQ_VSI_OVLAN_EMOD_MASK (0x03 <<\ + I40E_AQ_VSI_OVLAN_EMOD_SHIFT) +#define I40E_AQ_VSI_OVLAN_EMOD_SHOW_ALL 0x00 +#define I40E_AQ_VSI_OVLAN_EMOD_SHOW_UP 0x01 +#define I40E_AQ_VSI_OVLAN_EMOD_HIDE_ALL 0x02 +#define I40E_AQ_VSI_OVLAN_EMOD_NOTHING 0x03 +#define I40E_AQ_VSI_OVLAN_CTRL_ENA 0x04 + + u8 pvlan_reserved[2]; /* ingress egress up sections */ __le32 ingress_table; /* bitmap, 3 bits per up */ #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0