From patchwork Fri Jun 18 10:37:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 94467 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D7AABA0C46; Fri, 18 Jun 2021 12:46:04 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D4F134122F; Fri, 18 Jun 2021 12:42:01 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 4C84641219 for ; Fri, 18 Jun 2021 12:42:00 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15IAYfv6029381 for ; Fri, 18 Jun 2021 03:41:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=MJYcMzF/HZP4nxtG7SCGT2zbvF+iqea0cwiByOi2sDM=; b=eCGvHUnWD53GrmXhYInz1XdQY6/5lWHL9ngaKudbYiolzsLFkdTPTlpAKc/I4qnf7afg lZorvCQ1mzE2VGC4sdsY0NkUVygTupdQyeT6V4xjfUDQT5WT0qsUvy+1qNh/N9i964BM +xepuQxuqHu1jxPg9fhfut87R9rEezDYYC/bZJZXli7G8iZJJx8kL4yunBeAyjp27qTJ ePkm01Zwz2aH5HGLBUw8cPhbjMVA187ZonKBdKcdMDTardqInp1v0w1E6MknEnxuoLJy tgxqKB/UXF3svbBf+FO5T6jR+TDmAhKWKb/HFT5EsRQdQtD9N9C5LOpkT3mSN9Ykccjt qQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 398r750d9s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 18 Jun 2021 03:41:59 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 18 Jun 2021 03:41:58 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 18 Jun 2021 03:41:57 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id D6CBC5B6A0A; Fri, 18 Jun 2021 03:41:33 -0700 (PDT) From: Nithin Dabilpuram To: CC: , , , , , , , Date: Fri, 18 Jun 2021 16:07:37 +0530 Message-ID: <20210618103741.26526-59-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210618103741.26526-1-ndabilpuram@marvell.com> References: <20210306153404.10781-1-ndabilpuram@marvell.com> <20210618103741.26526-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 1DylLYPMRqXBktNdLBXl8BI2446kuQvM X-Proofpoint-GUID: 1DylLYPMRqXBktNdLBXl8BI2446kuQvM X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-18_04:2021-06-18, 2021-06-18 signatures=0 Subject: [dpdk-dev] [PATCH v3 58/62] net/cnxk: add time read/write/adjust operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Patch implements read/write/adjust time operations for cn9k and cn10k platforms. Signed-off-by: Sunil Kumar Kori --- drivers/net/cnxk/cnxk_ethdev.c | 3 ++ drivers/net/cnxk/cnxk_ethdev.h | 5 ++++ drivers/net/cnxk/cnxk_ptp.c | 63 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+) diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 0bef942..cac8ddf 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1250,6 +1250,9 @@ struct eth_dev_ops cnxk_eth_dev_ops = { .get_reg = cnxk_nix_dev_get_reg, .timesync_read_rx_timestamp = cnxk_nix_timesync_read_rx_timestamp, .timesync_read_tx_timestamp = cnxk_nix_timesync_read_tx_timestamp, + .timesync_read_time = cnxk_nix_timesync_read_time, + .timesync_write_time = cnxk_nix_timesync_write_time, + .timesync_adjust_time = cnxk_nix_timesync_adjust_time, }; static int diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 76df84a..4214365 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -317,6 +317,11 @@ int cnxk_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev, uint32_t flags); int cnxk_nix_timesync_read_tx_timestamp(struct rte_eth_dev *eth_dev, struct timespec *timestamp); +int cnxk_nix_timesync_read_time(struct rte_eth_dev *eth_dev, + struct timespec *ts); +int cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev, + const struct timespec *ts); +int cnxk_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta); int cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev); uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev); diff --git a/drivers/net/cnxk/cnxk_ptp.c b/drivers/net/cnxk/cnxk_ptp.c index 7b00f87..52f6eb1 100644 --- a/drivers/net/cnxk/cnxk_ptp.c +++ b/drivers/net/cnxk/cnxk_ptp.c @@ -56,6 +56,69 @@ cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev) } int +cnxk_nix_timesync_read_time(struct rte_eth_dev *eth_dev, struct timespec *ts) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_nix *nix = &dev->nix; + uint64_t clock, ns; + int rc; + + rc = roc_nix_ptp_clock_read(nix, &clock, NULL, false); + if (rc) + return rc; + + ns = rte_timecounter_update(&dev->systime_tc, clock); + *ts = rte_ns_to_timespec(ns); + return 0; +} + +int +cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev, + const struct timespec *ts) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + uint64_t ns; + + ns = rte_timespec_to_ns(ts); + /* Set the time counters to a new value. */ + dev->systime_tc.nsec = ns; + dev->rx_tstamp_tc.nsec = ns; + dev->tx_tstamp_tc.nsec = ns; + + return 0; +} + +int +cnxk_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + struct roc_nix *nix = &dev->nix; + int rc; + + /* Adjust the frequent to make tics increments in 10^9 tics per sec */ + if (delta < ROC_NIX_PTP_FREQ_ADJUST && + delta > -ROC_NIX_PTP_FREQ_ADJUST) { + rc = roc_nix_ptp_sync_time_adjust(nix, delta); + if (rc) + return rc; + + /* Since the frequency of PTP comp register is tuned, delta and + * freq mult calculation for deriving PTP_HI from timestamp + * counter should be done again. + */ + rc = cnxk_nix_tsc_convert(dev); + if (rc) + plt_err("Failed to calculate delta and freq mult"); + } + + dev->systime_tc.nsec += delta; + dev->rx_tstamp_tc.nsec += delta; + dev->tx_tstamp_tc.nsec += delta; + + return 0; +} + +int cnxk_nix_timesync_read_rx_timestamp(struct rte_eth_dev *eth_dev, struct timespec *timestamp, uint32_t flags) {