diff mbox series

[v2,41/58] net/bnxt: add support for wild card pattern match

Message ID 20210613000652.28191-42-ajit.khaparde@broadcom.com (mailing list archive)
State Accepted
Delegated to: Ajit Khaparde
Headers show
Series enhancements to host based flow table management | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Ajit Khaparde June 13, 2021, 12:06 a.m. UTC
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>

The computational field is enabled for wild card pattern support.
The template checks the computational field to add a flow as wild
card entry or exact match entry.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
 drivers/net/bnxt/tf_ulp/ulp_rte_parser.c       | 4 ++--
 drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 3 ++-
 2 files changed, 4 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
index 37dedbe243..3c45acd18f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
@@ -50,8 +50,8 @@  ulp_rte_parser_field_bitmap_update(struct ulp_rte_parser_params *params,
 		ULP_INDEX_BITMAP_SET(params->fld_bitmap.bits, idx);
 		/* Not exact match */
 		if (!ulp_bitmap_is_ones(field->mask, field->size))
-			ULP_BITMAP_SET(params->fld_bitmap.bits,
-				       BNXT_ULP_MATCH_TYPE_BITMASK_WM);
+			ULP_COMP_FLD_IDX_WR(params,
+					    BNXT_ULP_CF_IDX_WC_MATCH, 1);
 	} else {
 		ULP_INDEX_BITMAP_RESET(params->fld_bitmap.bits, idx);
 	}
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index d42933df66..5e839107a8 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -180,7 +180,8 @@  enum bnxt_ulp_cf_idx {
 	BNXT_ULP_CF_IDX_FID = 49,
 	BNXT_ULP_CF_IDX_HDR_SIG_ID = 50,
 	BNXT_ULP_CF_IDX_FLOW_SIG_ID = 51,
-	BNXT_ULP_CF_IDX_LAST = 52
+	BNXT_ULP_CF_IDX_WC_MATCH = 52,
+	BNXT_ULP_CF_IDX_LAST = 53
 };
 
 enum bnxt_ulp_cond_list_opc {