From patchwork Sun Jun 13 00:06:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Khaparde X-Patchwork-Id: 94131 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0BE71A0C41; Sun, 13 Jun 2021 02:12:46 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7C7E1411F3; Sun, 13 Jun 2021 02:08:28 +0200 (CEST) Received: from mail-pg1-f169.google.com (mail-pg1-f169.google.com [209.85.215.169]) by mails.dpdk.org (Postfix) with ESMTP id 377184111F for ; Sun, 13 Jun 2021 02:08:27 +0200 (CEST) Received: by mail-pg1-f169.google.com with SMTP id i34so5605691pgl.9 for ; Sat, 12 Jun 2021 17:08:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version; bh=Wmq4LsGLIewKC5KvETs7fMxTLmUPECYlK/JJCbtF2d4=; b=KniZydcWygDQmv1Uy+X3NkB0Srdo+VFZB3arWajuzSnlxrYEemvmEOTcjFtmsXJZrg yT1M9TogE0B/FgcryXEutOIWoK/b2f0GskB+mpgYRCCFBAAMxKBHCIW+Yd4Bz5i8HwOJ LDAHlfcnIlY/sHtGdnHGspwDbB5/ISxc3bLKI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version; bh=Wmq4LsGLIewKC5KvETs7fMxTLmUPECYlK/JJCbtF2d4=; b=PAbJdXywB6mra2wayq6wGpY5Z5RWKX2ClQr2NA1tgP5liV7UWSXQcqeRTEUGnSM1tc BkrSxh7NfnfUfoED0tfU5zFt5Hw4HsBdplRsuXIqgCYR8I42+iss/BFhX08C50/4QM0A hhXos8JUega1o14Vz/R2rvP8KSmhtVaevoac+0zCBVcWk1DiORkwl8HMzXkoyPvynVcr 5mpSe/0vm3XWCWgAt+foJAw27K2y+zgiQUhCIsNNZzn14h3pYtn5blx7Kqf3g0bzdC7w r3eHXtulcYKl0KCN2e69AH1jo1qKkBgi7DGS32FWPON/OjpSx+iD98oPSP746NczVNm0 tVLA== X-Gm-Message-State: AOAM5326nEE1um8e6GQgMD9ffFGR4q44jALlgqc61A9+7RQBYDuiuNMD 3Eshlo91TcNVLekPs/CPfYfoh5rha0bmPVfUIw7v1/nSjFkVtMjUA6Z+zolt5W1I1IvgFfRww97 PTfLQhKnzn8R6GYjb62YybSSNT9shoY1QI5g5KXrSMcQw0Ye5or1nzLKf3QrnIdk= X-Google-Smtp-Source: ABdhPJye3oF/6Ks1Gb80U7j6Uoj3X7Zshol7E/5WfKxgf9wlJpEDGQcGMGFDxrZgNq25sxlRGN3+Ig== X-Received: by 2002:a62:be18:0:b029:2aa:db3a:4c1d with SMTP id l24-20020a62be180000b02902aadb3a4c1dmr14073430pff.58.1623542905956; Sat, 12 Jun 2021 17:08:25 -0700 (PDT) Received: from localhost.localdomain ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id gg22sm12774609pjb.17.2021.06.12.17.08.24 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 12 Jun 2021 17:08:25 -0700 (PDT) From: Ajit Khaparde To: dev@dpdk.org Cc: Kishore Padmanabha , Venkat Duvvuru , Mike Baucom Date: Sat, 12 Jun 2021 17:06:34 -0700 Message-Id: <20210613000652.28191-41-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.21.1 (Apple Git-122.3) In-Reply-To: <20210613000652.28191-1-ajit.khaparde@broadcom.com> References: <20210530085929.29695-1-venkatkumar.duvvuru@broadcom.com> <20210613000652.28191-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.29 Subject: [dpdk-dev] [PATCH v2 40/58] net/bnxt: add partial header field processing X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kishore Padmanabha For support for wild card TCAM, some of the header fields have to be partially written, hence this new opcode is added. Signed-off-by: Kishore Padmanabha Signed-off-by: Venkat Duvvuru Reviewed-by: Mike Baucom Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/tf_ulp/ulp_mapper.c | 64 +++++++++++++------ .../net/bnxt/tf_ulp/ulp_template_db_enum.h | 13 ++-- 2 files changed, 51 insertions(+), 26 deletions(-) diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c index c231f765e6..df8041e897 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c +++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c @@ -927,7 +927,7 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, uint32_t val_size = 0, field_size = 0; uint64_t hdr_bit, act_bit, regval; uint16_t write_idx = blob->write_idx; - uint16_t idx, size_idx, bitlen; + uint16_t idx, size_idx, bitlen, offset; uint8_t *val = NULL; uint8_t tmpval[16]; uint8_t bit; @@ -1340,6 +1340,46 @@ ulp_mapper_field_process(struct bnxt_ulp_mapper_parms *parms, break; case BNXT_ULP_FIELD_SRC_REJECT: return -EINVAL; + case BNXT_ULP_FIELD_SRC_SUB_HF: + if (!ulp_operand_read(fld_src_oper, + (uint8_t *)&idx, sizeof(uint16_t))) { + BNXT_TF_DBG(ERR, "%s operand read failed\n", name); + return -EINVAL; + } + idx = tfp_be_to_cpu_16(idx); + /* get the index from the global field list */ + if (ulp_mapper_glb_field_tbl_get(parms, idx, &bit)) { + BNXT_TF_DBG(ERR, "invalid ulp_glb_field_tbl idx %d\n", + idx); + return -EINVAL; + } + + /* get the offset next */ + if (!ulp_operand_read(&fld_src_oper[sizeof(uint16_t)], + (uint8_t *)&offset, sizeof(uint16_t))) { + BNXT_TF_DBG(ERR, "%s operand read failed\n", name); + return -EINVAL; + } + offset = tfp_be_to_cpu_16(offset); + if ((offset + bitlen) > + ULP_BYTE_2_BITS(parms->hdr_field[bit].size) || + ULP_BITS_IS_BYTE_NOT_ALIGNED(offset)) { + BNXT_TF_DBG(ERR, "Hdr field[%s] oob\n", name); + return -EINVAL; + } + offset = ULP_BITS_2_BYTE_NR(offset); + + /* write the value into blob */ + if (is_key) + val = &parms->hdr_field[bit].spec[offset]; + else + val = &parms->hdr_field[bit].mask[offset]; + + if (!ulp_blob_push(blob, val, bitlen)) { + BNXT_TF_DBG(ERR, "%s push to blob failed\n", name); + return -EINVAL; + } + break; default: BNXT_TF_DBG(ERR, "%s invalid field opcode 0x%x at %d\n", name, fld_src, write_idx); @@ -1630,25 +1670,9 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms, return rc; } -#define BNXT_ULP_WC_TCAM_SLICE_SIZE 80 /* internal function to post process the key/mask blobs for wildcard tcam tbl */ -static void ulp_mapper_wc_tcam_tbl_post_process(struct ulp_blob *blob, - uint32_t len) +static void ulp_mapper_wc_tcam_tbl_post_process(struct ulp_blob *blob) { - uint8_t mode[2] = {0x0, 0x0}; - uint32_t mode_len = len / BNXT_ULP_WC_TCAM_SLICE_SIZE; - uint32_t size, idx; - - /* Add the mode bits to the key and mask*/ - if (mode_len == 2) - mode[1] = 2; - else if (mode_len > 2) - mode[1] = 3; - - size = BNXT_ULP_WC_TCAM_SLICE_SIZE + ULP_BYTE_2_BITS(sizeof(mode)); - for (idx = 0; idx < mode_len; idx++) - ulp_blob_insert(blob, (size * idx), mode, - ULP_BYTE_2_BITS(sizeof(mode))); ulp_blob_perform_64B_word_swap(blob); ulp_blob_perform_64B_byte_swap(blob); } @@ -1736,8 +1760,8 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms, /* For wild card tcam perform the post process to swap the blob */ if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM) { - ulp_mapper_wc_tcam_tbl_post_process(&key, tbl->key_bit_size); - ulp_mapper_wc_tcam_tbl_post_process(&mask, tbl->key_bit_size); + ulp_mapper_wc_tcam_tbl_post_process(&key); + ulp_mapper_wc_tcam_tbl_post_process(&mask); } if (tbl->tbl_opcode == BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE) { diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h index 4a1faacfbe..d42933df66 100644 --- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h +++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h @@ -278,12 +278,13 @@ enum bnxt_ulp_field_src { BNXT_ULP_FIELD_SRC_ACT_PROP_SZ = 6, BNXT_ULP_FIELD_SRC_GLB_RF = 7, BNXT_ULP_FIELD_SRC_HF = 8, - BNXT_ULP_FIELD_SRC_HDR_BIT = 9, - BNXT_ULP_FIELD_SRC_ACT_BIT = 10, - BNXT_ULP_FIELD_SRC_FIELD_BIT = 11, - BNXT_ULP_FIELD_SRC_SKIP = 12, - BNXT_ULP_FIELD_SRC_REJECT = 13, - BNXT_ULP_FIELD_SRC_LAST = 14 + BNXT_ULP_FIELD_SRC_SUB_HF = 9, + BNXT_ULP_FIELD_SRC_HDR_BIT = 10, + BNXT_ULP_FIELD_SRC_ACT_BIT = 11, + BNXT_ULP_FIELD_SRC_FIELD_BIT = 12, + BNXT_ULP_FIELD_SRC_SKIP = 13, + BNXT_ULP_FIELD_SRC_REJECT = 14, + BNXT_ULP_FIELD_SRC_LAST = 15 }; enum bnxt_ulp_generic_tbl_opc {