From: Sunil Kumar Kori <skori@marvell.com>
Patch implements read raw clock operation for cn9k and
cn10k.
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
---
doc/guides/nics/features/cnxk.ini | 2 ++
drivers/net/cnxk/cnxk_ethdev.c | 1 +
drivers/net/cnxk/cnxk_ethdev.h | 1 +
drivers/net/cnxk/cnxk_ptp.c | 17 +++++++++++++++++
4 files changed, 21 insertions(+)
@@ -32,6 +32,8 @@ L4 checksum offload = Y
Inner L3 checksum = Y
Inner L4 checksum = Y
Packet type parsing = Y
+Timesync = Y
+Timestamp offload = Y
Basic stats = Y
Stats per queue = Y
Extended stats = Y
@@ -1236,6 +1236,7 @@ struct eth_dev_ops cnxk_eth_dev_ops = {
.timesync_read_time = cnxk_nix_timesync_read_time,
.timesync_write_time = cnxk_nix_timesync_write_time,
.timesync_adjust_time = cnxk_nix_timesync_adjust_time,
+ .read_clock = cnxk_nix_read_clock,
};
static int
@@ -307,6 +307,7 @@ int cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
const struct timespec *ts);
int cnxk_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta);
int cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev);
+int cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock);
uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev);
@@ -4,6 +4,23 @@
#include "cnxk_ethdev.h"
+int
+cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock)
+{
+ struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+
+ /* This API returns the raw PTP HI clock value. Since LFs do not
+ * have direct access to PTP registers and it requires mbox msg
+ * to AF for this value. In fastpath reading this value for every
+ * packet (which involes mbox call) becomes very expensive, hence
+ * we should be able to derive PTP HI clock value from tsc by
+ * using freq_mult and clk_delta calculated during configure stage.
+ */
+ *clock = (rte_get_tsc_cycles() + dev->clk_delta) * dev->clk_freq_mult;
+
+ return 0;
+}
+
/* This function calculates two parameters "clk_freq_mult" and
* "clk_delta" which is useful in deriving PTP HI clock from
* timestamp counter (tsc) value.