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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT014.mail.protection.outlook.com (10.13.177.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4150.30 via Frontend Transport; Tue, 1 Jun 2021 07:11:53 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 1 Jun 2021 07:11:51 +0000 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Date: Tue, 1 Jun 2021 10:11:21 +0300 Message-ID: <20210601071122.1612432-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601071122.1612432-1-michaelba@nvidia.com> References: <20210601071122.1612432-1-michaelba@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3833df6c-8a5f-4be0-f24b-08d924cc8892 X-MS-TrafficTypeDiagnostic: BY5PR12MB4904: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4303; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jun 2021 07:11:53.0956 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3833df6c-8a5f-4be0-f24b-08d924cc8892 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT014.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4904 Subject: [dpdk-dev] [PATCH 3/4] vdpa/mlx5: fix constant type in QP creation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The mlx5_vdpa_event_qp_create function makes shifting to the numeric constant 1, then multiplies it by another constant and finally assigns it into a uint64_t variable. The numeric constant type is an int with a 32-bit sign. if after shifting , its MSB (bit of sign) will change, the uint64 variable will get into it a different value than what the function intended it to get. Set the numeric constant 1 to be uint64_t in the first place. Fixes: 8395927cdfaf ("vdpa/mlx5: prepare HW queues") Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/vdpa/mlx5/mlx5_vdpa_event.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c index 88f6a4256d..3541c652ce 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c @@ -629,8 +629,8 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n, attr.wq_umem_id = eqp->umem_obj->umem_id; attr.wq_umem_offset = 0; attr.dbr_umem_id = eqp->umem_obj->umem_id; - attr.dbr_address = (1 << log_desc_n) * MLX5_WSEG_SIZE; attr.ts_format = mlx5_ts_format_conv(priv->qp_ts_format); + attr.dbr_address = RTE_BIT64(log_desc_n) * MLX5_WSEG_SIZE; eqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr); if (!eqp->sw_qp) { DRV_LOG(ERR, "Failed to create SW QP(%u).", rte_errno);