Message ID | 20210601071122.1612432-2-michaelba@nvidia.com (mailing list archive) |
---|---|
State | Superseded, archived |
Delegated to: | Thomas Monjalon |
Headers |
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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jun 2021 07:11:51.1950 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 92cfd506-00ef-452c-e202-08d924cc876d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT003.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3000 Subject: [dpdk-dev] [PATCH 2/4] compress/mlx5: fix constant size in QP creation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> |
Series |
[1/4] regex/mlx5: fix size of setup constants
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|
Checks
Context | Check | Description |
---|---|---|
ci/checkpatch | success | coding style OK |
Commit Message
Michael Baum
June 1, 2021, 7:11 a.m. UTC
The mlx5_compress_qp_setup function makes shifting to the numeric
constant 1, then sends it as a parameter to rte_calloc function.
The rte_calloc function expects to get size_t (64 bits, unsigned) and
instead gets a 32-bit variable, because the numeric constant size is a
32-bit.
In case the shift is greater than 32 the variable will lose its value
even though the function can get 64-bit argument.
Change the size of the numeric constant 1 to 64-bit.
Fixes: 8619fcd5161b ("compress/mlx5: support queue pair operations")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
---
drivers/compress/mlx5/mlx5_compress.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
From: Michael Baum: > The mlx5_compress_qp_setup function makes shifting to the numeric > constant 1, then sends it as a parameter to rte_calloc function. > > The rte_calloc function expects to get size_t (64 bits, unsigned) and instead > gets a 32-bit variable, because the numeric constant size is a 32-bit. > In case the shift is greater than 32 the variable will lose its value even though > the function can get 64-bit argument. > > Change the size of the numeric constant 1 to 64-bit. > > Fixes: 8619fcd5161b ("compress/mlx5: support queue pair operations") > Cc: stable@dpdk.org > > Signed-off-by: Michael Baum <michaelba@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
01/06/2021 09:11, Michael Baum: > The mlx5_compress_qp_setup function makes shifting to the numeric > constant 1, then sends it as a parameter to rte_calloc function. > > The rte_calloc function expects to get size_t (64 bits, unsigned) and No on 32-bit systems, size_t is 32 bits. > instead gets a 32-bit variable, because the numeric constant size is a > 32-bit. Most of the patches of this series say "constant" where it is a variable. > In case the shift is greater than 32 the variable will lose its value > even though the function can get 64-bit argument. > > Change the size of the numeric constant 1 to 64-bit. [...] > - opaq_buf = rte_calloc(__func__, 1u << log_ops_n, > + opaq_buf = rte_calloc(__func__, RTE_BIT64(log_ops_n),
External email: Use caution opening links or attachments > -----Original Message----- > From: Thomas Monjalon <thomas@monjalon.net> > Sent: Wednesday, June 23, 2021 9:48 AM > To: Michael Baum <michaelba@nvidia.com> > Cc: dev@dpdk.org; stable@dpdk.org; Matan Azrad <matan@nvidia.com>; > Raslan Darawsheh <rasland@nvidia.com>; Slava Ovsiienko > <viacheslavo@nvidia.com> > Subject: Re: [dpdk-stable] [PATCH 2/4] compress/mlx5: fix constant size in > QP creation > > External email: Use caution opening links or attachments > > > 01/06/2021 09:11, Michael Baum: > > The mlx5_compress_qp_setup function makes shifting to the numeric > > constant 1, then sends it as a parameter to rte_calloc function. > > > > The rte_calloc function expects to get size_t (64 bits, unsigned) and > > No on 32-bit systems, size_t is 32 bits. Thanks for the comment, I'll send v2. > > instead gets a 32-bit variable, because the numeric constant size is a > > 32-bit. > > Most of the patches of this series say "constant" where it is a variable. > > > In case the shift is greater than 32 the variable will lose its value > > even though the function can get 64-bit argument. > > > > Change the size of the numeric constant 1 to 64-bit. > [...] > > - opaq_buf = rte_calloc(__func__, 1u << log_ops_n, > > + opaq_buf = rte_calloc(__func__, RTE_BIT64(log_ops_n), > >
diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 80c564f10b..90d009c56b 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -209,7 +209,7 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, return -rte_errno; } dev->data->queue_pairs[qp_id] = qp; - opaq_buf = rte_calloc(__func__, 1u << log_ops_n, + opaq_buf = rte_calloc(__func__, RTE_BIT64(log_ops_n), sizeof(struct mlx5_gga_compress_opaque), sizeof(struct mlx5_gga_compress_opaque)); if (opaq_buf == NULL) {