diff mbox series

[23/28] raw/cnxk_bphy: add baseband phy skeleton driver

Message ID 20210531214142.30167-24-tduszynski@marvell.com (mailing list archive)
State Superseded
Delegated to: Thomas Monjalon
Headers show
Series add support for baseband phy | expand

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Tomasz Duszynski May 31, 2021, 9:41 p.m. UTC
Add baseband phy sekelton driver. Baseband phy is a hardware subsystem
accelerating 5G/LTE related tasks.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst      |  14 +++-
 drivers/raw/cnxk_bphy/cnxk_bphy.c     | 113 ++++++++++++++++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h |  23 ++++++
 drivers/raw/cnxk_bphy/meson.build     |   1 +
 usertools/dpdk-devbind.py             |   4 +-
 5 files changed, 153 insertions(+), 2 deletions(-)
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
diff mbox series

Patch

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 1b117a0e8..4e7f18c2a 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -17,6 +17,8 @@  Features
 The BPHY CGX/RPM implements following features in the rawdev API:
 
 - Access to BPHY CGX/RPM via set of predefined messages.
+- Access to BPHY memory
+- Custom interrupt handlers
 
 Device Setup
 ------------
@@ -33,6 +35,16 @@  To perform data transfer use standard ``rte_rawdev_enqueue_buffers()`` and
 ``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible
 responses hence dequeueing is not always necessary.
 
+Other features are realized by custom API calls:
+
+- BPHY memory ranges are obtained with single ``rte_pmd_bphy_intr_mem_get()``,
+- interrupt  initialization, registration, unregistration and termination are
+  done with ``rte_pmd_bphy_intr_init()``, ``rte_pmd_bphy_intr_register()``,
+  ``rte_pmd_bphy_intr_unregister()`` and ``rte_pmd_bphy_intr_fini()``,
+  respectively. In order to register an interrupt prior initialization is
+  required. The same way, the subsystem should be terminated when no longer
+  used.
+
 Self test
 ---------
 
@@ -40,7 +52,7 @@  On EAL initialization, BPHY CGX/RPM devices will be probed and populated into
 the raw devices. The rawdev ID of the device can be obtained using invocation
 of ``rte_rawdev_get_dev_id("NAME:x")`` from the test application, where:
 
-- NAME is the desired subsystem: use "BPHY_CGX" for
+- NAME is the desired subsystem: use "BPHY" for regular, and "BPHY_CGX" for
   RFOE module,
 - x is the device's bus id specified in "bus:device.func" (BDF) format.
 
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
new file mode 100644
index 000000000..51affed78
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -0,0 +1,113 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell International Ltd.
+ */
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_dev.h>
+#include <rte_eal.h>
+#include <rte_lcore.h>
+#include <rte_pci.h>
+#include <rte_rawdev.h>
+#include <rte_rawdev_pmd.h>
+
+#include <roc_api.h>
+
+#include "cnxk_bphy_irq.h"
+
+static const struct rte_pci_id pci_bphy_map[] = {
+	{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_BPHY)},
+	{
+		.vendor_id = 0,
+	},
+};
+
+static const struct rte_rawdev_ops bphy_rawdev_ops = {
+};
+
+static void
+bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev)
+{
+	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "BPHY:%x:%02x.%x",
+		 pci_dev->addr.bus, pci_dev->addr.devid,
+		 pci_dev->addr.function);
+}
+
+static int
+bphy_rawdev_probe(struct rte_pci_driver *pci_drv,
+		  struct rte_pci_device *pci_dev)
+{
+	struct bphy_device *bphy_dev = NULL;
+	char name[RTE_RAWDEV_NAME_MAX_LEN];
+	struct rte_rawdev *bphy_rawdev;
+	int ret;
+
+	RTE_SET_USED(pci_drv);
+
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+		return 0;
+
+	if (!pci_dev->mem_resource[0].addr) {
+		plt_err("BARs have invalid values: BAR0 %p\n BAR2 %p",
+			pci_dev->mem_resource[0].addr,
+			pci_dev->mem_resource[2].addr);
+		return -ENODEV;
+	}
+
+	ret = roc_plt_init();
+	if (ret)
+		return ret;
+
+	bphy_rawdev_get_name(name, pci_dev);
+	bphy_rawdev = rte_rawdev_pmd_allocate(name, sizeof(*bphy_dev),
+					      rte_socket_id());
+	if (bphy_rawdev == NULL) {
+		plt_err("Failed to allocate rawdev");
+		return -ENOMEM;
+	}
+
+	bphy_rawdev->dev_ops = &bphy_rawdev_ops;
+	bphy_rawdev->device = &pci_dev->device;
+	bphy_rawdev->driver_name = pci_dev->driver->driver.name;
+
+	bphy_dev = (struct bphy_device *)bphy_rawdev->dev_private;
+	bphy_dev->mem.res0 = pci_dev->mem_resource[0];
+	bphy_dev->mem.res2 = pci_dev->mem_resource[2];
+
+	return 0;
+}
+
+static int
+bphy_rawdev_remove(struct rte_pci_device *pci_dev)
+{
+	char name[RTE_RAWDEV_NAME_MAX_LEN];
+	struct rte_rawdev *rawdev;
+
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+		return 0;
+
+	if (pci_dev == NULL) {
+		plt_err("invalid pci_dev");
+		return -EINVAL;
+	}
+
+	rawdev = rte_rawdev_pmd_get_named_dev(name);
+	if (rawdev == NULL) {
+		plt_err("invalid device name (%s)", name);
+		return -EINVAL;
+	}
+
+	bphy_rawdev_get_name(name, pci_dev);
+
+	return rte_rawdev_pmd_release(rawdev);
+}
+
+static struct rte_pci_driver cnxk_bphy_rawdev_pmd = {
+	.id_table = pci_bphy_map,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
+	.probe = bphy_rawdev_probe,
+	.remove = bphy_rawdev_remove,
+};
+
+RTE_PMD_REGISTER_PCI(bphy_rawdev_pci_driver, cnxk_bphy_rawdev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(bphy_rawdev_pci_driver, pci_bphy_map);
+RTE_PMD_REGISTER_KMOD_DEP(bphy_rawdev_pci_driver, "vfio-pci");
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
new file mode 100644
index 000000000..77169b1b7
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -0,0 +1,23 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _CNXK_BPHY_IRQ_
+#define _CNXK_BPHY_IRQ_
+
+#include <rte_bus_pci.h>
+#include <rte_dev.h>
+
+#include <roc_api.h>
+
+struct bphy_mem {
+	struct rte_mem_resource res0;
+	struct rte_mem_resource res2;
+};
+
+struct bphy_device {
+	struct roc_bphy_irq_chip *irq_chip;
+	struct bphy_mem mem;
+};
+
+#endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build
index 2fab7c0ec..23d46f11d 100644
--- a/drivers/raw/cnxk_bphy/meson.build
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -4,6 +4,7 @@ 
 
 deps += ['bus_pci', 'common_cnxk', 'rawdev']
 sources = files(
+    'cnxk_bphy.c',
     'cnxk_bphy_cgx.c',
     'cnxk_bphy_cgx_test.c'
 )
diff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py
index be43befd6..ed1bb906f 100755
--- a/usertools/dpdk-devbind.py
+++ b/usertools/dpdk-devbind.py
@@ -45,6 +45,8 @@ 
                  'SVendor': None, 'SDevice': None}
 octeontx2_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4',
                  'SVendor': None, 'SDevice': None}
+cnxk_bphy = {'Class': '08', 'Vendor': '177d', 'Device': 'a089'
+             'SVendor': None, 'SDevice': None}
 cnxk_bphy_cgx = {'Class': '08', 'Vendor': '177d', 'Device': 'a059', 'a060'
                  'SVendor': None, 'SDevice': None}
 
@@ -71,7 +73,7 @@ 
 mempool_devices = [cavium_fpa, octeontx2_npa]
 compress_devices = [cavium_zip]
 regex_devices = [octeontx2_ree]
-misc_devices = [cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
+misc_devices = [cnxk_bphy, cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
                 intel_ntb_skx, intel_ntb_icx,
                 octeontx2_dma]