From patchwork Mon May 31 14:10:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arkadiusz Kusztal X-Patchwork-Id: 93624 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 07BECA0524; Mon, 31 May 2021 16:10:54 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6F73840E32; Mon, 31 May 2021 16:10:49 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id 2EBC94003F for ; Mon, 31 May 2021 16:10:46 +0200 (CEST) IronPort-SDR: sIOln6XY/6B+b3FqKkgsXg0my2RD2Hi151Yf4jsCMGig5ksdJzfqNAfAXjBr7Y7Ii+lAs7T37j y+2l7KtzBBbQ== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="201492202" X-IronPort-AV: E=Sophos;i="5.83,237,1616482800"; d="scan'208";a="201492202" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2021 07:10:44 -0700 IronPort-SDR: 50j9qnt1RntzLfJ3s6XWNcWeBY+z67VOu+aQ6tSHAlAfzzK2xOTejxt2rZVo2EfGGQPtKKTyXx R7Sidbii2k4w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,237,1616482800"; d="scan'208";a="548760052" Received: from silpixa00400308.ir.intel.com ([10.237.214.61]) by orsmga004.jf.intel.com with ESMTP; 31 May 2021 07:10:43 -0700 From: Arek Kusztal To: dev@dpdk.org Cc: gakhil@marvell.com, fiona.trahe@intel.com, roy.fan.zhang@intel.com, Arek Kusztal Date: Mon, 31 May 2021 15:10:13 +0100 Message-Id: <20210531141027.13289-2-arkadiuszx.kusztal@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210531141027.13289-1-arkadiuszx.kusztal@intel.com> References: <20210531141027.13289-1-arkadiuszx.kusztal@intel.com> Subject: [dpdk-dev] [PATCH 01/15] common/qat: rework qp per service function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Different generations of Intel QuickAssist Technology devices may differ in approach to allocate queues. Queue pair number function therefore needs to be more generic. Signed-off-by: Arek Kusztal --- drivers/common/qat/qat_qp.c | 15 ++++++++++----- drivers/common/qat/qat_qp.h | 2 +- drivers/compress/qat/qat_comp_pmd.c | 9 ++++----- drivers/crypto/qat/qat_asym_pmd.c | 9 ++++----- drivers/crypto/qat/qat_sym_pmd.c | 9 ++++----- 5 files changed, 23 insertions(+), 21 deletions(-) diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c index 4a8078541c..aa64d2e168 100644 --- a/drivers/common/qat/qat_qp.c +++ b/drivers/common/qat/qat_qp.c @@ -145,14 +145,19 @@ static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr, rte_spinlock_t *lock); -int qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data, +int qat_qps_per_service(struct qat_pci_device *qat_dev, enum qat_service_type service) { - int i, count; - - for (i = 0, count = 0; i < ADF_MAX_QPS_ON_ANY_SERVICE; i++) - if (qp_hw_data[i].service_type == service) + int i = 0, count = 0, max_ops_per_srv = 0; + const struct qat_qp_hw_data* + sym_hw_qps = qat_gen_config[qat_dev->qat_dev_gen] + .qp_hw_data[service]; + + max_ops_per_srv = ADF_MAX_QPS_ON_ANY_SERVICE; + for (; i < max_ops_per_srv; i++) + if (sym_hw_qps[i].service_type == service) count++; + return count; } diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h index 74f7e7daee..d353e8552b 100644 --- a/drivers/common/qat/qat_qp.h +++ b/drivers/common/qat/qat_qp.h @@ -98,7 +98,7 @@ qat_qp_setup(struct qat_pci_device *qat_dev, struct qat_qp_config *qat_qp_conf); int -qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data, +qat_qps_per_service(struct qat_pci_device *qat_dev, enum qat_service_type service); int diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c index 8de41f6b6e..6eb1ae3a21 100644 --- a/drivers/compress/qat/qat_comp_pmd.c +++ b/drivers/compress/qat/qat_comp_pmd.c @@ -106,6 +106,7 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, struct qat_qp **qp_addr = (struct qat_qp **)&(dev->data->queue_pairs[qp_id]); struct qat_comp_dev_private *qat_private = dev->data->dev_private; + struct qat_pci_device *qat_dev = qat_private->qat_dev; const struct qat_qp_hw_data *comp_hw_qps = qat_gen_config[qat_private->qat_dev->qat_dev_gen] .qp_hw_data[QAT_SERVICE_COMPRESSION]; @@ -117,7 +118,7 @@ qat_comp_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, if (ret < 0) return ret; } - if (qp_id >= qat_qps_per_service(comp_hw_qps, + if (qp_id >= qat_qps_per_service(qat_dev, QAT_SERVICE_COMPRESSION)) { QAT_LOG(ERR, "qp_id %u invalid for this device", qp_id); return -EINVAL; @@ -592,13 +593,11 @@ qat_comp_dev_info_get(struct rte_compressdev *dev, struct rte_compressdev_info *info) { struct qat_comp_dev_private *comp_dev = dev->data->dev_private; - const struct qat_qp_hw_data *comp_hw_qps = - qat_gen_config[comp_dev->qat_dev->qat_dev_gen] - .qp_hw_data[QAT_SERVICE_COMPRESSION]; + struct qat_pci_device *qat_dev = comp_dev->qat_dev; if (info != NULL) { info->max_nb_queue_pairs = - qat_qps_per_service(comp_hw_qps, + qat_qps_per_service(qat_dev, QAT_SERVICE_COMPRESSION); info->feature_flags = dev->feature_flags; info->capabilities = comp_dev->qat_dev_capabilities; diff --git a/drivers/crypto/qat/qat_asym_pmd.c b/drivers/crypto/qat/qat_asym_pmd.c index a2c8aca2c1..f0c8ed1bcf 100644 --- a/drivers/crypto/qat/qat_asym_pmd.c +++ b/drivers/crypto/qat/qat_asym_pmd.c @@ -54,12 +54,10 @@ static void qat_asym_dev_info_get(struct rte_cryptodev *dev, struct rte_cryptodev_info *info) { struct qat_asym_dev_private *internals = dev->data->dev_private; - const struct qat_qp_hw_data *asym_hw_qps = - qat_gen_config[internals->qat_dev->qat_dev_gen] - .qp_hw_data[QAT_SERVICE_ASYMMETRIC]; + struct qat_pci_device *qat_dev = internals->qat_dev; if (info != NULL) { - info->max_nb_queue_pairs = qat_qps_per_service(asym_hw_qps, + info->max_nb_queue_pairs = qat_qps_per_service(qat_dev, QAT_SERVICE_ASYMMETRIC); info->feature_flags = dev->feature_flags; info->capabilities = internals->qat_dev_capabilities; @@ -128,6 +126,7 @@ static int qat_asym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id, struct qat_qp **qp_addr = (struct qat_qp **)&(dev->data->queue_pairs[qp_id]); struct qat_asym_dev_private *qat_private = dev->data->dev_private; + struct qat_pci_device *qat_dev = qat_private->qat_dev; const struct qat_qp_hw_data *asym_hw_qps = qat_gen_config[qat_private->qat_dev->qat_dev_gen] .qp_hw_data[QAT_SERVICE_ASYMMETRIC]; @@ -139,7 +138,7 @@ static int qat_asym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id, if (ret < 0) return ret; } - if (qp_id >= qat_qps_per_service(asym_hw_qps, QAT_SERVICE_ASYMMETRIC)) { + if (qp_id >= qat_qps_per_service(qat_dev, QAT_SERVICE_ASYMMETRIC)) { QAT_LOG(ERR, "qp_id %u invalid for this device", qp_id); return -EINVAL; } diff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c index b9601c6c3a..549345b6fa 100644 --- a/drivers/crypto/qat/qat_sym_pmd.c +++ b/drivers/crypto/qat/qat_sym_pmd.c @@ -90,13 +90,11 @@ static void qat_sym_dev_info_get(struct rte_cryptodev *dev, struct rte_cryptodev_info *info) { struct qat_sym_dev_private *internals = dev->data->dev_private; - const struct qat_qp_hw_data *sym_hw_qps = - qat_gen_config[internals->qat_dev->qat_dev_gen] - .qp_hw_data[QAT_SERVICE_SYMMETRIC]; + struct qat_pci_device *qat_dev = internals->qat_dev; if (info != NULL) { info->max_nb_queue_pairs = - qat_qps_per_service(sym_hw_qps, QAT_SERVICE_SYMMETRIC); + qat_qps_per_service(qat_dev, QAT_SERVICE_SYMMETRIC); info->feature_flags = dev->feature_flags; info->capabilities = internals->qat_dev_capabilities; info->driver_id = qat_sym_driver_id; @@ -164,6 +162,7 @@ static int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id, struct qat_qp **qp_addr = (struct qat_qp **)&(dev->data->queue_pairs[qp_id]); struct qat_sym_dev_private *qat_private = dev->data->dev_private; + struct qat_pci_device *qat_dev = qat_private->qat_dev; const struct qat_qp_hw_data *sym_hw_qps = qat_gen_config[qat_private->qat_dev->qat_dev_gen] .qp_hw_data[QAT_SERVICE_SYMMETRIC]; @@ -175,7 +174,7 @@ static int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t qp_id, if (ret < 0) return ret; } - if (qp_id >= qat_qps_per_service(sym_hw_qps, QAT_SERVICE_SYMMETRIC)) { + if (qp_id >= qat_qps_per_service(qat_dev, QAT_SERVICE_SYMMETRIC)) { QAT_LOG(ERR, "qp_id %u invalid for this device", qp_id); return -EINVAL; }