[v7,3/3] net/i40e: enable PCI bus master after reset

Message ID 20210524012346.496560-4-haiyue.wang@intel.com (mailing list archive)
State Accepted, archived
Delegated to: David Marchand
Headers
Series fix PF reset causes VF memory request failure |

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Context Check Description
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ci/intel-Testing success Testing PASS
ci/iol-mellanox-Functional fail Functional Testing issues
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ci/iol-intel-Functional fail Functional Testing issues

Commit Message

Wang, Haiyue May 24, 2021, 1:23 a.m. UTC
  The VF reset can be triggered by the PF reset event, then the PCI bus
master will be cleared, the VF will be not allowed to issue any Memory
or I/O Requests.

So after the reset event is detected, always enable the PCI bus master.
And if failed, the device or system may be in an invalid state, so keep
the VF reset state to mark it as I/O error.

Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
---
 drivers/net/i40e/i40e_ethdev_vf.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)
  

Comments

Xing, Beilei June 4, 2021, 1:58 a.m. UTC | #1
> -----Original Message-----
> From: Wang, Haiyue <haiyue.wang@intel.com>
> Sent: Monday, May 24, 2021 9:24 AM
> To: dev@dpdk.org
> Cc: Zhang, Qi Z <qi.z.zhang@intel.com>; Wang, Liang-min <liang-
> min.wang@intel.com>; david.marchand@redhat.com; Wang, Haiyue
> <haiyue.wang@intel.com>; Xing, Beilei <beilei.xing@intel.com>
> Subject: [PATCH v7 3/3] net/i40e: enable PCI bus master after reset
> 
> The VF reset can be triggered by the PF reset event, then the PCI bus master
> will be cleared, the VF will be not allowed to issue any Memory or I/O
> Requests.
> 
> So after the reset event is detected, always enable the PCI bus master.
> And if failed, the device or system may be in an invalid state, so keep the VF
> reset state to mark it as I/O error.
> 
> Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
> ---
>  drivers/net/i40e/i40e_ethdev_vf.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/i40e/i40e_ethdev_vf.c
> b/drivers/net/i40e/i40e_ethdev_vf.c
> index cb898bdb68..385ebedcd3 100644
> --- a/drivers/net/i40e/i40e_ethdev_vf.c
> +++ b/drivers/net/i40e/i40e_ethdev_vf.c
> @@ -1213,7 +1213,6 @@ i40evf_check_vf_reset_done(struct rte_eth_dev
> *dev)
>  	if (i >= MAX_RESET_WAIT_CNT)
>  		return -1;
> 
> -	vf->vf_reset = false;
>  	vf->pend_msg &= ~PFMSG_RESET_IMPENDING;
> 
>  	return 0;
> @@ -1392,6 +1391,7 @@ i40evf_handle_pf_event(struct rte_eth_dev *dev,
> uint8_t *msg,
>  	switch (pf_msg->event) {
>  	case VIRTCHNL_EVENT_RESET_IMPENDING:
>  		PMD_DRV_LOG(DEBUG,
> "VIRTCHNL_EVENT_RESET_IMPENDING event");
> +		vf->vf_reset = true;
>  		rte_eth_dev_callback_process(dev,
>  				RTE_ETH_EVENT_INTR_RESET, NULL);
>  		break;
> @@ -2468,6 +2468,7 @@ i40evf_dev_close(struct rte_eth_dev *dev)  {
>  	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data-
> >dev_private);
>  	struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data-
> >dev_private);
> +	struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
>  	int ret;
> 
>  	if (rte_eal_process_type() != RTE_PROC_PRIMARY) @@ -2490,6
> +2491,16 @@ i40evf_dev_close(struct rte_eth_dev *dev)
>  	i40e_shutdown_adminq(hw);
>  	i40evf_disable_irq0(hw);
> 
> +	/*
> +	 * If the VF is reset via VFLR, the device will be knocked out of bus
> +	 * master mode, and the driver will fail to recover from the reset. Fix
> +	 * this by enabling bus mastering after every reset. In a non-VFLR
> case,
> +	 * the bus master bit will not be disabled, and this call will have no
> +	 * effect.
> +	 */
> +	if (vf->vf_reset && !rte_pci_set_bus_master(pci_dev, true))
> +		vf->vf_reset = false;
> +
>  	rte_free(vf->vf_res);
>  	vf->vf_res = NULL;
>  	rte_free(vf->aq_resp);
> --
> 2.31.1

Acked-by: Beilei Xing <beilei.xing@intel.com>
  

Patch

diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c
index cb898bdb68..385ebedcd3 100644
--- a/drivers/net/i40e/i40e_ethdev_vf.c
+++ b/drivers/net/i40e/i40e_ethdev_vf.c
@@ -1213,7 +1213,6 @@  i40evf_check_vf_reset_done(struct rte_eth_dev *dev)
 	if (i >= MAX_RESET_WAIT_CNT)
 		return -1;
 
-	vf->vf_reset = false;
 	vf->pend_msg &= ~PFMSG_RESET_IMPENDING;
 
 	return 0;
@@ -1392,6 +1391,7 @@  i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
 	switch (pf_msg->event) {
 	case VIRTCHNL_EVENT_RESET_IMPENDING:
 		PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
+		vf->vf_reset = true;
 		rte_eth_dev_callback_process(dev,
 				RTE_ETH_EVENT_INTR_RESET, NULL);
 		break;
@@ -2468,6 +2468,7 @@  i40evf_dev_close(struct rte_eth_dev *dev)
 {
 	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 	struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
+	struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 	int ret;
 
 	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
@@ -2490,6 +2491,16 @@  i40evf_dev_close(struct rte_eth_dev *dev)
 	i40e_shutdown_adminq(hw);
 	i40evf_disable_irq0(hw);
 
+	/*
+	 * If the VF is reset via VFLR, the device will be knocked out of bus
+	 * master mode, and the driver will fail to recover from the reset. Fix
+	 * this by enabling bus mastering after every reset. In a non-VFLR case,
+	 * the bus master bit will not be disabled, and this call will have no
+	 * effect.
+	 */
+	if (vf->vf_reset && !rte_pci_set_bus_master(pci_dev, true))
+		vf->vf_reset = false;
+
 	rte_free(vf->vf_res);
 	vf->vf_res = NULL;
 	rte_free(vf->aq_resp);