From patchwork Tue May 11 11:44:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ferruh Yigit X-Patchwork-Id: 93156 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4EC3CA0A0E; Tue, 11 May 2021 13:45:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 35D2940140; Tue, 11 May 2021 13:45:01 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id EA7B24003E; Tue, 11 May 2021 13:44:59 +0200 (CEST) IronPort-SDR: MLpDVhWgsLedUNHsRjMTno8vIijOf2pD3cKpUMQvipfFKgxwBK0uVqnaD2Nghy3ZIEChHyDasl ZMBrybe0XWew== X-IronPort-AV: E=McAfee;i="6200,9189,9980"; a="199100181" X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="199100181" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2021 04:44:59 -0700 IronPort-SDR: hOGxQW2Otwhz8LG0dph8uN8rAXYxnxuPzs/F6+GFp0uTvUvIfG+Mcq7RVfa63IQwe6awA8z15T bg/N+dSsXk4g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,290,1613462400"; d="scan'208";a="609457368" Received: from silpixa00399752.ir.intel.com (HELO silpixa00399752.ger.corp.intel.com) ([10.237.222.27]) by orsmga005.jf.intel.com with ESMTP; 11 May 2021 04:44:57 -0700 From: Ferruh Yigit To: Rasesh Mody , Shahed Shaikh Cc: Ferruh Yigit , dev@dpdk.org, stable@dpdk.org, Kevin Traynor , Ajit Khaparde Date: Tue, 11 May 2021 12:44:51 +0100 Message-Id: <20210511114454.3923410-1-ferruh.yigit@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210510150319.1496105-1-ferruh.yigit@intel.com> References: <20210510150319.1496105-1-ferruh.yigit@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 1/4] net/bnx2x: fix build with gcc11 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Reproduced with '--buildtype=debugoptimized' config, compiler version: gcc (GCC) 12.0.0 20210509 (experimental) Build error: In file included from ../drivers/net/bnx2x/bnx2x_rxtx.c:8: ../drivers/net/bnx2x/bnx2x_rxtx.c: In function ‘bnx2x_upd_rx_prod_fast’: ../drivers/net/bnx2x/bnx2x.h:1528:35: warning: ‘rx_prods’ is used uninitialized [-Wuninitialized] #define REG_WR32(sc, offset, val) bnx2x_reg_write32(sc, (offset), val) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../drivers/net/bnx2x/bnx2x.h:1531:33: note: in expansion of macro ‘REG_WR32’ 1531 | #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) | ^~~~~~~~ ../drivers/net/bnx2x/bnx2x_rxtx.c:331:9: note: in expansion of macro ‘REG_WR’ 331 | REG_WR(sc, fp->ustorm_rx_prods_offset, val[0]); | ^~~~~~ ../drivers/net/bnx2x/bnx2x_rxtx.c:324:40: note: ‘rx_prods’ declared here 324 | struct ustorm_eth_rx_producers rx_prods = { 0 }; | ^~~~~~~~ REG_WR32 requires 'uint32_t', use union instead of cast to 'uint32_t'. Fixes: 38dff79ba736 ("net/bnx2x: update HSI") Cc: stable@dpdk.org Signed-off-by: Ferruh Yigit Acked-by: Kevin Traynor --- Cc: rmody@marvell.com Cc: Kevin Traynor Cc: Ajit Khaparde v2: * fix struct initialization as '{0}' -> '{{0}}' --- drivers/net/bnx2x/bnx2x_rxtx.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/bnx2x/bnx2x_rxtx.c b/drivers/net/bnx2x/bnx2x_rxtx.c index 57e2ce504587..2b1760229051 100644 --- a/drivers/net/bnx2x/bnx2x_rxtx.c +++ b/drivers/net/bnx2x/bnx2x_rxtx.c @@ -321,14 +321,15 @@ static inline void bnx2x_upd_rx_prod_fast(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint16_t rx_bd_prod, uint16_t rx_cq_prod) { - struct ustorm_eth_rx_producers rx_prods = { 0 }; - uint32_t *val = NULL; + union { + struct ustorm_eth_rx_producers rx_prods; + uint32_t val; + } val = { {0} }; - rx_prods.bd_prod = rx_bd_prod; - rx_prods.cqe_prod = rx_cq_prod; + val.rx_prods.bd_prod = rx_bd_prod; + val.rx_prods.cqe_prod = rx_cq_prod; - val = (uint32_t *)&rx_prods; - REG_WR(sc, fp->ustorm_rx_prods_offset, val[0]); + REG_WR(sc, fp->ustorm_rx_prods_offset, val.val); } static uint16_t