From patchwork Sat May 8 01:20:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alvin Zhang X-Patchwork-Id: 93052 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D9479A0A0A; Sat, 8 May 2021 03:20:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 799CB40140; Sat, 8 May 2021 03:20:44 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id 1D6224013F; Sat, 8 May 2021 03:20:41 +0200 (CEST) IronPort-SDR: jxxM7N3l8kO15V5v8jVD7l3bg4FBdI6cUoiRaeUOhgnlyD1bFBd6H+Vgp9v7DZL0VkSt27BFSE AzNbrocidiXQ== X-IronPort-AV: E=McAfee;i="6200,9189,9977"; a="260119441" X-IronPort-AV: E=Sophos;i="5.82,282,1613462400"; d="scan'208";a="260119441" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 May 2021 18:20:39 -0700 IronPort-SDR: TCZbjAZPXCxxXPwZG8VBXkcf+aHTrsvsOo8LZsT7bsj5Kzq2y1F38RKrt8kDMVkJc+jaZaf+YL HRtJ9zk+hEDg== X-IronPort-AV: E=Sophos;i="5.82,282,1613462400"; d="scan'208";a="453304954" Received: from shwdenpg235.ccr.corp.intel.com ([10.240.182.60]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 May 2021 18:20:37 -0700 From: Alvin Zhang To: qi.z.zhang@intel.com, ferruh.yigit@intel.com Cc: dev@dpdk.org, Alvin Zhang , stable@dpdk.org Date: Sat, 8 May 2021 09:20:32 +0800 Message-Id: <20210508012032.14860-1-alvinx.zhang@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20210425092639.1428-1-alvinx.zhang@intel.com> References: <20210425092639.1428-1-alvinx.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2] net/ice: fix txq vector path selection X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" If Tx vector mode is disabled, the txq vector mode should be disabled too. This patch adds checking of Tx vector mode before enabling txq vector mode. Fixes: 28f9002ab67f ("net/ice: add Tx AVX512 offload path") Cc: stable@dpdk.org Signed-off-by: Alvin Zhang --- v2: Update commit log. --- drivers/net/ice/ice_rxtx.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c index 92fbbc1..49abcb2 100644 --- a/drivers/net/ice/ice_rxtx.c +++ b/drivers/net/ice/ice_rxtx.c @@ -3303,13 +3303,6 @@ if (tx_check_ret >= 0 && rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { ad->tx_vec_allowed = true; - for (i = 0; i < dev->data->nb_tx_queues; i++) { - txq = dev->data->tx_queues[i]; - if (txq && ice_txq_vec_setup(txq)) { - ad->tx_vec_allowed = false; - break; - } - } if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 && @@ -3329,6 +3322,15 @@ if (!use_avx512 && tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) ad->tx_vec_allowed = false; + if (ad->tx_vec_allowed) { + for (i = 0; i < dev->data->nb_tx_queues; i++) { + txq = dev->data->tx_queues[i]; + if (txq && ice_txq_vec_setup(txq)) { + ad->tx_vec_allowed = false; + break; + } + } + } } else { ad->tx_vec_allowed = false; }