From patchwork Wed May 5 09:49:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bing Zhao X-Patchwork-Id: 92896 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 66292A0524; Wed, 5 May 2021 11:50:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A4621410F3; Wed, 5 May 2021 11:50:34 +0200 (CEST) Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam08on2042.outbound.protection.outlook.com [40.107.101.42]) by mails.dpdk.org (Postfix) with ESMTP id E17BF410EE for ; Wed, 5 May 2021 11:50:32 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=cBpWDK0BaE/ARd111LLub9zXV5q2EgKK4cO7ho41KzK4AZ4LgK1qz89SHfZnOOdAOdpRWM0wmxlt+ylYcsR5KN95mfq5C6c+F1GuyhgrdamEQCQz3j/uTSojboed2SCo+RthIV3V0zNfpgR1TLuOrjirVp/hz2t0/YGrPVC/uO36Zgea91UkuOkAVZtIOhObtebmRpwQz7vZOB4M6GWKz7vwqpixUguux3aRA6xWVbFR/pEbVeXieUNboyiAfYWeZVewxnQBdj1Mt83h2Q3ZR3LWQePtNWTJW+wLSOTUcKqYJ/J4A75veepyCiDa5RQqC3Gc/hBkOgKN4PjUJKLkTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=U27bZsj+xwl2QwJdY3qqXs1Bm38ANEWUWu7oWAAWjXg=; b=hUAji+ZQm0JWp39GmIVwsLp4g95Xo7N+G86W6demiV8o7jL6gN6u2unOJNEbOZLCRnikx4bbBZaCsOGCjr7ocZjCIbrcNaQm8KHhOATIIKYNsJPJz4K6csagsOr2yDDQW9J4KcuFuflhi1DW+jlVyHOr1DXAfXSelXII8QEvU8al+u4sgoH/IsYoznEdvBXEefluOUdy4R3y/ncwsVl6LOaXOhVImB0vKq3SX88kPJA1K91P36/0gzYOJ9mSeXoYqlzpN50OTWU+tJtMiFDNmJdBupthULP7xKCm2Ey0VLsg1fwadQckseBJEnzP3pTjB4Pxle1s0rXsfQOWloDlWA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=U27bZsj+xwl2QwJdY3qqXs1Bm38ANEWUWu7oWAAWjXg=; b=MgXRqGRoMi9CqsnxOwsGNPiXYWk0a0LkNbJZL0LkJGxmgNlsR36BlkDD7laBojE/YVW3ZmhFUFg5yEHleDgZqFEPzaLM7K9JcqryPB6EIYuA6ho9CgXFr56tfhwBAQnR5DmjQEL7fSFtfipvPXYRT8ypaECAM/i95cFl4MxNieBq2vQjYFnHDAn8/7SAZEifhHoxRNYS2R1nzxhDSCTPOh8CC7q5u0YdMjyOWvC9TDKmABE3Ci/3J0mvKJyEzNKzM8OgL4FlXYSUeThYUCMMdvWQCJrhXt6ps4Jm20LUS8ornvV8ypXG4Hxl9QT0K/keW3sLEV7omzi8g++PJVBXyQ== Received: from BN9PR03CA0571.namprd03.prod.outlook.com (2603:10b6:408:10d::6) by CH2PR12MB3784.namprd12.prod.outlook.com (2603:10b6:610:21::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.43; Wed, 5 May 2021 09:50:30 +0000 Received: from BN8NAM11FT057.eop-nam11.prod.protection.outlook.com (2603:10b6:408:10d:cafe::5) by BN9PR03CA0571.outlook.office365.com (2603:10b6:408:10d::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.24 via Frontend Transport; Wed, 5 May 2021 09:50:30 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT057.mail.protection.outlook.com (10.13.177.49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4108.25 via Frontend Transport; Wed, 5 May 2021 09:50:30 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 5 May 2021 09:50:28 +0000 From: Bing Zhao To: , , CC: , , Date: Wed, 5 May 2021 12:49:54 +0300 Message-ID: <20210505095009.40250-3-bingz@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210505095009.40250-1-bingz@nvidia.com> References: <20210427153811.11554-1-bingz@nvidia.com> <20210505095009.40250-1-bingz@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 2b008eae-e577-4d00-5cb6-08d90fab3834 X-MS-TrafficTypeDiagnostic: CH2PR12MB3784: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MSp1nuHno73i6/QgcLzOtrB99lTIZVOmzL8wjBs51IfQ2Ycak0XWoba5QWkP6NVOyA2Rr7UsqoWqbbI4+MiUxEzelrkr+LkDnavIQw+++QY2ycF+qfh0ImlMU7JHPZNB3q3L7JZCOd2oZN3Xlf5n4EGChT8vz/yxLYwqbxErEudEize1ukVGopSiZYTYsUwsG3w1EobntRQBnsTYUtSrWbKrc7AFhxzP/kQNwNsfUF01ajPWAC7JIYF7S8FBbuM4/BxMCifUuMHLeqMoJ4fn91wine3dVOXjT6DDWtx4OU6x2ktFAVbE/aL7sMa5qU4tu9G4sE4sLOeRviEXdlTU+SRtrZYe6sNzz0yqcS4q3BkNXMV9tUIQZ3n1wCiVGAe+wrqGS3h/b65HUNpi79l8TW+FwQdIy57ZubSFZTvXkcpkpDktoNbPl6UMM3n3nqROlkwiqc07PL+KWdNamnIiaH8k5SITlfBGaD+p/r4uP8cu7F38dStsaXTd2FllyuYio8VeSf082Z2ZtyDDGS1/Ghm+/FC7b47Jhz2MC//Jg8XMpxJ4/W2YVlGRt/XDA0l3cMMjZnST4dnLmvDGz0XigFsHHRIEENNIa8pglM3MWntkFaMe+pP6t/XzayHM0K/hb84Ztavx1na9JRRfNt02qzGq4AsJhs486pCw1BkcZFo= X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(346002)(396003)(39860400002)(136003)(376002)(36840700001)(46966006)(47076005)(82310400003)(8936002)(1076003)(55016002)(5660300002)(8676002)(478600001)(83380400001)(86362001)(356005)(36860700001)(36756003)(7636003)(82740400003)(54906003)(70206006)(336012)(110136005)(36906005)(26005)(2616005)(70586007)(107886003)(6666004)(4326008)(6286002)(16526019)(7696005)(316002)(186003)(426003)(2906002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 May 2021 09:50:30.4686 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b008eae-e577-4d00-5cb6-08d90fab3834 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT057.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB3784 Subject: [dpdk-dev] [PATCH v6 02/17] common/mlx5: add CT offload capability checking X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" During startup, the ASO connection tracking offload capability could be queried via HCA_CAP_QUERY command. If the HW doesn't support ASO CT, the value would be 0 by default. The following initialization should be skipped and the creation of the CT object should return a failure directly. The following CT creation should also check this capability. With the old driver, the pre-processing macro should be used in order to make the compiling pass. Signed-off-by: Bing Zhao --- drivers/common/mlx5/linux/meson.build | 2 ++ drivers/common/mlx5/mlx5_devx_cmds.c | 3 +++ drivers/common/mlx5/mlx5_devx_cmds.h | 1 + drivers/common/mlx5/mlx5_prm.h | 3 +++ 4 files changed, 9 insertions(+) diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build index 3334bd5cb2..007834a49b 100644 --- a/drivers/common/mlx5/linux/meson.build +++ b/drivers/common/mlx5/linux/meson.build @@ -189,6 +189,8 @@ has_sym_args = [ 'MLX5_WQE_UMR_CTRL_FLAG_INLINE' ], [ 'HAVE_MLX5_DR_FLOW_DUMP_RULE', 'infiniband/mlx5dv.h', 'mlx5dv_dump_dr_rule' ], + [ 'HAVE_MLX5_DR_ACTION_ASO_CT', 'infiniband/mlx5dv.h', + 'MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR' ], ] config = configuration_data() foreach arg:has_sym_args diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 1b54c05313..7a0efa59e5 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -783,6 +783,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled); attr->umr_modify_entity_size_disabled = MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled); + attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, + general_obj_types) & + MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); if (attr->qos.sup) { MLX5_SET(query_hca_cap_in, in, op_mod, MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 5681e03fee..e6f9b90293 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -137,6 +137,7 @@ struct mlx5_hca_attr { uint32_t qp_ts_format:2; uint32_t regex:1; uint32_t reg_c_preserve:1; + uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ uint32_t regexp_num_of_engines; uint32_t log_max_ft_sampler_num:8; uint32_t geneve_tlv_opt; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 683ab40338..b385b6f518 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1139,6 +1139,8 @@ enum { (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO) #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \ (1ULL << MLX5_OBJ_TYPE_GENEVE_TLV_OPT) +#define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \ + (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD) enum { MLX5_HCA_CAP_OPMOD_GET_MAX = 0, @@ -2487,6 +2489,7 @@ enum { MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022, MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024, MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025, + MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031, }; struct mlx5_ifc_general_obj_in_cmd_hdr_bits {