From patchwork Wed May 5 07:33:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 92861 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F2C36A0524; Wed, 5 May 2021 09:35:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8F14D41147; Wed, 5 May 2021 09:34:15 +0200 (CEST) Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) by mails.dpdk.org (Postfix) with ESMTP id 8D6644113C for ; Wed, 5 May 2021 09:34:12 +0200 (CEST) Received: by mail-wm1-f41.google.com with SMTP id u5-20020a7bc0450000b02901480e40338bso2458925wmc.1 for ; Wed, 05 May 2021 00:34:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wVCIIWfG1ewbxMCYkXKpJdBDMDGLo9RmM8jL1tSe0MA=; b=Ny83Ft2aMhXHDo498ry2oW337stgAtgYbVzNwbYWBXWJkCnrim4YlWVmBnxfpW0vvp T7EjkzR2HK9j2DKavamgZLH65PqtMW39vH8MT61aDELpR64nSUcN4IG5nJ9LuJpKijgz jZhuRgxzVW5XjJ9L18FjcudTzhj2gj8gCvz0r1q7qk9aRlo9NMl83ykFr+wKq80WMCsw VU8hAvyvL5TpXTpa7S2p/DL+NO5DHW1b5c9XkpIyOLqBmUi+XChO6c3mIwuQEgxnP2ec F4MBbm/KRtQF6XVFhBjE2OxAm2wdNv4tvxU7VKzJ3Vji4hWV4KKrDJimXQRSaW1T4Buz 2D6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wVCIIWfG1ewbxMCYkXKpJdBDMDGLo9RmM8jL1tSe0MA=; b=jay/R3zi11uvS8zFbkcW6FzB7JHZ5L1v9+Ubc4V5fVcBYPHclAKF3XciA8lXPjgTwg 8mP67ww4/Et0D+h2BBOuHFRZqa04EVtHUVI3dWNUAeqCLcCwc3XJzcPSKrlEZkAHrvHX HXBdPs08RSv6KVYS67Mf9p+wOU+NqwDX/2L3vVhKgvnqKtZZVsquYd17fgS1cz3ZZ1A9 ITD9WoxrBNVhXCvO7xm27Y40C1NpZkYnqOyQh8bjk1EQmiD5juKgD0ZO54KiyZEBF5JO ghrBFNauaM55L/n+EBt1VfdmiO7DGGPC0vwEnvmckCdWMbLU5Pj1zD4Y1mAQju82/v6s z1kA== X-Gm-Message-State: AOAM531qhPwEaoe76iP20pR8CFQabplHZLQN7GUzdxFQtw7Bvo03QX7o 3sThiU8/w6b9q2tWSsfmb4GHKVUWIaVYk0nA X-Google-Smtp-Source: ABdhPJyJKu+q/KWIdRAkNpPIEbQq3mOMxSDUE7dmFG/FAZgOwZll9jbEeU6K0XxmnOgwRXEMyvKNSw== X-Received: by 2002:a1c:c5:: with SMTP id 188mr28816417wma.5.1620200052045; Wed, 05 May 2021 00:34:12 -0700 (PDT) Received: from DESKTOP-U5LNN3J.localdomain (89-79-189-199.dynamic.chello.pl. [89.79.189.199]) by smtp.gmail.com with ESMTPSA id t17sm4679856wmq.12.2021.05.05.00.34.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 May 2021 00:34:11 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazon.com, gtzalik@amazon.com, igorch@amazon.com, upstream@semihalf.com, Michal Krawczyk , Amit Bernstein Date: Wed, 5 May 2021 09:33:36 +0200 Message-Id: <20210505073348.6394-11-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210505073348.6394-1-mk@semihalf.com> References: <20210430125725.28796-1-mk@semihalf.com> <20210505073348.6394-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 10/22] net/ena/base: use rte_prefetch0_write X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" As in the v20.11 rte_prefetch0_write API was added, it should be used in the platform file for the definition of the macro prefetchw, instead of using simply prefetch0. Signed-off-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Amit Bernstein --- drivers/net/ena/base/ena_plat_dpdk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h index 067909f745..6902efae08 100644 --- a/drivers/net/ena/base/ena_plat_dpdk.h +++ b/drivers/net/ena/base/ena_plat_dpdk.h @@ -290,7 +290,7 @@ extern rte_atomic32_t ena_alloc_cnt; #define might_sleep() #define prefetch(x) rte_prefetch0(x) -#define prefetchw(x) prefetch(x) +#define prefetchw(x) rte_prefetch0_write(x) #define lower_32_bits(x) ((uint32_t)(x)) #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))