From patchwork Tue May 4 00:26:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92686 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DA4DDA0562; Tue, 4 May 2021 02:28:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1FC3F41143; Tue, 4 May 2021 02:28:26 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B198541143 for ; Tue, 4 May 2021 02:28:24 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440AGT0002336 for ; Mon, 3 May 2021 17:28:24 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=4H3Ezz0pv06UMIJ3vTjZYB4amzmQZFPkqOobl/N+WPA=; b=AtJmeRwXiyDBQMCs0/o3tzPSCnRjSvdxuUibLt9BzPzoXBXAfczUKeOUsJY38tHXiN85 GZ+z7SFCz5c+D3Ry+PqvRZGCe8MEDBLBgkJ+1gUtFMWIvFQKHqknBT+tNkolLk17+Uo5 28zKzr6GRGRXpq2VjYoNWnshVqSY3AphRLCQQv6fDhmIelEwzpAhqba69KdJnXM4HWIW +w9kPggWteeXEv1tDCNrQ/CBOegASIBVe4iJsNNByMb3GP6YC78QgWhGoYMuR0MxV5tA TSgVVWQjwqZSgxgItdSLDgqiiQeBjKl4aGQtXU2ugVGy97+DYpNU4fA8q8lVMIHXQYL6 sg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05k6jy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:24 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:21 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id B4DF03F703F; Mon, 3 May 2021 17:28:20 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:56:58 +0530 Message-ID: <20210504002726.525-9-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: xBaV1XYU6OUyHz1vhIX9Da8E-bglYJrQ X-Proofpoint-ORIG-GUID: xBaV1XYU6OUyHz1vhIX9Da8E-bglYJrQ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 08/35] event/cnxk: add event queue config functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add setup and release functions for event queues i.e. SSO HWGRPs. Signed-off-by: Shijith Thotton Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_eventdev.c | 2 ++ drivers/event/cnxk/cn9k_eventdev.c | 2 ++ drivers/event/cnxk/cnxk_eventdev.c | 19 +++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 3 +++ 4 files changed, 26 insertions(+) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 779a2e026..557f26b8f 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -62,6 +62,8 @@ static struct rte_eventdev_ops cn10k_sso_dev_ops = { .dev_infos_get = cn10k_sso_info_get, .dev_configure = cn10k_sso_dev_configure, .queue_def_conf = cnxk_sso_queue_def_conf, + .queue_setup = cnxk_sso_queue_setup, + .queue_release = cnxk_sso_queue_release, .port_def_conf = cnxk_sso_port_def_conf, }; diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index d042f58da..eba1bfbf0 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -70,6 +70,8 @@ static struct rte_eventdev_ops cn9k_sso_dev_ops = { .dev_infos_get = cn9k_sso_info_get, .dev_configure = cn9k_sso_dev_configure, .queue_def_conf = cnxk_sso_queue_def_conf, + .queue_setup = cnxk_sso_queue_setup, + .queue_release = cnxk_sso_queue_release, .port_def_conf = cnxk_sso_port_def_conf, }; diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index 3eab1ed29..e22479a19 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -86,6 +86,25 @@ cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id, queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL; } +int +cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id, + const struct rte_event_queue_conf *queue_conf) +{ + struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev); + + plt_sso_dbg("Queue=%d prio=%d", queue_id, queue_conf->priority); + /* Normalize <0-255> to <0-7> */ + return roc_sso_hwgrp_set_priority(&dev->sso, queue_id, 0xFF, 0xFF, + queue_conf->priority / 32); +} + +void +cnxk_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id) +{ + RTE_SET_USED(event_dev); + RTE_SET_USED(queue_id); +} + void cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id, struct rte_event_port_conf *port_conf) diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 59d96a08f..426219c85 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -45,6 +45,9 @@ void cnxk_sso_info_get(struct cnxk_sso_evdev *dev, int cnxk_sso_dev_validate(const struct rte_eventdev *event_dev); void cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id, struct rte_event_queue_conf *queue_conf); +int cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id, + const struct rte_event_queue_conf *queue_conf); +void cnxk_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id); void cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id, struct rte_event_port_conf *port_conf);