From patchwork Tue May 4 00:27:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92712 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5AA21A0562; Tue, 4 May 2021 02:31:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8166C411AB; Tue, 4 May 2021 02:29:40 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B3EFD4111F for ; Tue, 4 May 2021 02:29:38 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440QWtI026649 for ; Mon, 3 May 2021 17:29:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Ux8UPAEKVRmN/cl7dCFWVf7Kaar1hHC1ysMQsyst6ko=; b=J6GNb/NUXEPFNA+SHMiZc5UO8rhAs/QgzHYtFwbJYiOysVXsoT0RQC+jiBjFGuYpp+RP 5BtZt36O/WDfOa9Ci51/77RXdkrsVd1bjDoNkIXMzjCQZk9fMQHgUwtEICn4xqYhlhee UoGNQi7Ydb5/u+NABTh9LX8kOOxlvu6gj03XsiKfXnLQfDLinn7ts7qfvTEFGUnujTfm y6TasGdxz9iFDJalOImWPu6ewJ7alcJDufIluG4aZBSThvbLASpdA5aaDFbPV0ZjKka3 Ev/RUyRg8UDAFoQtQkIU5wH/qutc8Mn7/xTUw8T6TkidWPdwz2Oi2G6SaPYakLs2E8mL FQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnud-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:29:37 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:36 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:29:36 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 2D71B3F703F; Mon, 3 May 2021 17:29:34 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:24 +0530 Message-ID: <20210504002726.525-35-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 1LMWxft54NHC5DHwhhou8Ttd3Bau17pF X-Proofpoint-ORIG-GUID: 1LMWxft54NHC5DHwhhou8Ttd3Bau17pF X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 34/35] event/cnxk: add timer adapter start and stop X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add event timer adapter start and stop functions. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- drivers/event/cnxk/cnxk_tim_evdev.c | 71 ++++++++++++++++++++++++++++- 1 file changed, 70 insertions(+), 1 deletion(-) diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index a73ca33d8..19b71b4f5 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -246,6 +246,73 @@ cnxk_tim_ring_free(struct rte_event_timer_adapter *adptr) return 0; } +static void +cnxk_tim_calibrate_start_tsc(struct cnxk_tim_ring *tim_ring) +{ +#define CNXK_TIM_CALIB_ITER 1E6 + uint32_t real_bkt, bucket; + int icount, ecount = 0; + uint64_t bkt_cyc; + + for (icount = 0; icount < CNXK_TIM_CALIB_ITER; icount++) { + real_bkt = plt_read64(tim_ring->base + TIM_LF_RING_REL) >> 44; + bkt_cyc = cnxk_tim_cntvct(); + bucket = (bkt_cyc - tim_ring->ring_start_cyc) / + tim_ring->tck_int; + bucket = bucket % (tim_ring->nb_bkts); + tim_ring->ring_start_cyc = + bkt_cyc - (real_bkt * tim_ring->tck_int); + if (bucket != real_bkt) + ecount++; + } + tim_ring->last_updt_cyc = bkt_cyc; + plt_tim_dbg("Bucket mispredict %3.2f distance %d\n", + 100 - (((double)(icount - ecount) / (double)icount) * 100), + bucket - real_bkt); +} + +static int +cnxk_tim_ring_start(const struct rte_event_timer_adapter *adptr) +{ + struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv; + struct cnxk_tim_evdev *dev = cnxk_tim_priv_get(); + int rc; + + if (dev == NULL) + return -ENODEV; + + rc = roc_tim_lf_enable(&dev->tim, tim_ring->ring_id, + &tim_ring->ring_start_cyc, NULL); + if (rc < 0) + return rc; + + tim_ring->tck_int = NSEC2TICK(tim_ring->tck_nsec, cnxk_tim_cntfrq()); + tim_ring->tot_int = tim_ring->tck_int * tim_ring->nb_bkts; + tim_ring->fast_div = rte_reciprocal_value_u64(tim_ring->tck_int); + tim_ring->fast_bkt = rte_reciprocal_value_u64(tim_ring->nb_bkts); + + cnxk_tim_calibrate_start_tsc(tim_ring); + + return rc; +} + +static int +cnxk_tim_ring_stop(const struct rte_event_timer_adapter *adptr) +{ + struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv; + struct cnxk_tim_evdev *dev = cnxk_tim_priv_get(); + int rc; + + if (dev == NULL) + return -ENODEV; + + rc = roc_tim_lf_disable(&dev->tim, tim_ring->ring_id); + if (rc < 0) + plt_err("Failed to disable timer ring"); + + return rc; +} + static int cnxk_tim_stats_get(const struct rte_event_timer_adapter *adapter, struct rte_event_timer_adapter_stats *stats) @@ -278,13 +345,14 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, struct cnxk_tim_evdev *dev = cnxk_tim_priv_get(); RTE_SET_USED(flags); - RTE_SET_USED(ops); if (dev == NULL) return -ENODEV; cnxk_tim_ops.init = cnxk_tim_ring_create; cnxk_tim_ops.uninit = cnxk_tim_ring_free; + cnxk_tim_ops.start = cnxk_tim_ring_start; + cnxk_tim_ops.stop = cnxk_tim_ring_stop; cnxk_tim_ops.get_info = cnxk_tim_ring_info_get; if (dev->enable_stats) { @@ -295,6 +363,7 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, /* Store evdev pointer for later use. */ dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev; *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT; + *ops = &cnxk_tim_ops; return 0; }