From patchwork Tue May 4 00:27:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92711 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 217FEA0562; Tue, 4 May 2021 02:31:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BA7B54115A; Tue, 4 May 2021 02:29:37 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3763A4115A for ; Tue, 4 May 2021 02:29:36 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440P26P025320 for ; Mon, 3 May 2021 17:29:35 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=VLerbvCYDRMQyLw9SUPECMAGfCDV9Uh6w8+xs8tjtKs=; b=G/PxdE/SMOqSAxrtleyNYhCu6guxdWpGfRBEPap2Ex5Q01YcH62AOw7T/Pd9+TmQH3aj NWCLTdSnzyBVB74iIlp9OEAIFolKqvhhTlS7gF//mIyVVVdk/pVHQRYDy1dL4LXqvUJT rCFvcaO8Vvn+aGpZQ8YPqaYqimcPm63pnTGcpCcz8nXPEL3sg4mWYGuVqK6Ynzz92yaX 1VBFyztdMme/GwThx5DvSwCs0PqFgaqpb3txAnuadvNrC4a4QRjQyvi3GFuB8qsFYi6K +w1eQrhbMqBgiVhZ3gskKpMJixQcEdDNP9SF2kn2Bb3pdwsYHsO5pg2N6VYInUrB2DEk bA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnu8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:29:35 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:29:33 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:29:33 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 77A833F703F; Mon, 3 May 2021 17:29:32 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Tue, 4 May 2021 05:57:23 +0530 Message-ID: <20210504002726.525-34-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: a5rt2uOiBDVzFTEbjydngCYkKmbV5jJS X-Proofpoint-ORIG-GUID: a5rt2uOiBDVzFTEbjydngCYkKmbV5jJS X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 33/35] event/cnxk: add timer stats get and reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add event timer adapter statistics get and reset functions. Stats are disabled by default and can be enabled through devargs. Example: --dev "0002:1e:00.0,tim_stats_ena=1" Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- doc/guides/eventdevs/cnxk.rst | 9 +++++ drivers/event/cnxk/cn10k_eventdev.c | 3 +- drivers/event/cnxk/cn9k_eventdev.c | 3 +- drivers/event/cnxk/cnxk_tim_evdev.c | 50 ++++++++++++++++++++++++---- drivers/event/cnxk/cnxk_tim_evdev.h | 38 ++++++++++++++------- drivers/event/cnxk/cnxk_tim_worker.c | 11 ++++-- 6 files changed, 91 insertions(+), 23 deletions(-) diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst index a8199aac7..11145dd7d 100644 --- a/doc/guides/eventdevs/cnxk.rst +++ b/doc/guides/eventdevs/cnxk.rst @@ -115,6 +115,15 @@ Runtime Config Options -a 0002:0e:00.0,tim_chnk_slots=1023 +- ``TIM enable arm/cancel statistics`` + + The ``tim_stats_ena`` devargs can be used to enable arm and cancel stats of + event timer adapter. + + For example:: + + -a 0002:0e:00.0,tim_stats_ena=1 + - ``TIM limit max rings reserved`` The ``tim_rings_lmt`` devargs can be used to limit the max number of TIM diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index cadc792a7..bf4052c76 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -505,4 +505,5 @@ RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=" CN10K_SSO_GW_MODE "=" CNXK_TIM_DISABLE_NPA "=1" CNXK_TIM_CHNK_SLOTS "=" - CNXK_TIM_RINGS_LMT "="); + CNXK_TIM_RINGS_LMT "=" + CNXK_TIM_STATS_ENA "=1"); diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index e503f6b1c..0684417ea 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -574,4 +574,5 @@ RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=" CN9K_SSO_SINGLE_WS "=1" CNXK_TIM_DISABLE_NPA "=1" CNXK_TIM_CHNK_SLOTS "=" - CNXK_TIM_RINGS_LMT "="); + CNXK_TIM_RINGS_LMT "=" + CNXK_TIM_STATS_ENA "=1"); diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index 62a15a4a1..a73ca33d8 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -81,21 +81,25 @@ cnxk_tim_set_fp_ops(struct cnxk_tim_ring *tim_ring) { uint8_t prod_flag = !tim_ring->prod_type_sp; - /* [DFB/FB] [SP][MP]*/ - const rte_event_timer_arm_burst_t arm_burst[2][2] = { -#define FP(_name, _f2, _f1, flags) [_f2][_f1] = cnxk_tim_arm_burst_##_name, + /* [STATS] [DFB/FB] [SP][MP]*/ + const rte_event_timer_arm_burst_t arm_burst[2][2][2] = { +#define FP(_name, _f3, _f2, _f1, flags) \ + [_f3][_f2][_f1] = cnxk_tim_arm_burst_##_name, TIM_ARM_FASTPATH_MODES #undef FP }; - const rte_event_timer_arm_tmo_tick_burst_t arm_tmo_burst[2] = { -#define FP(_name, _f1, flags) [_f1] = cnxk_tim_arm_tmo_tick_burst_##_name, + const rte_event_timer_arm_tmo_tick_burst_t arm_tmo_burst[2][2] = { +#define FP(_name, _f2, _f1, flags) \ + [_f2][_f1] = cnxk_tim_arm_tmo_tick_burst_##_name, TIM_ARM_TMO_FASTPATH_MODES #undef FP }; - cnxk_tim_ops.arm_burst = arm_burst[tim_ring->ena_dfb][prod_flag]; - cnxk_tim_ops.arm_tmo_tick_burst = arm_tmo_burst[tim_ring->ena_dfb]; + cnxk_tim_ops.arm_burst = + arm_burst[tim_ring->enable_stats][tim_ring->ena_dfb][prod_flag]; + cnxk_tim_ops.arm_tmo_tick_burst = + arm_tmo_burst[tim_ring->enable_stats][tim_ring->ena_dfb]; cnxk_tim_ops.cancel_burst = cnxk_tim_timer_cancel_burst; } @@ -159,6 +163,7 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) tim_ring->nb_timers = rcfg->nb_timers; tim_ring->chunk_sz = dev->chunk_sz; tim_ring->disable_npa = dev->disable_npa; + tim_ring->enable_stats = dev->enable_stats; if (tim_ring->disable_npa) { tim_ring->nb_chunks = @@ -241,6 +246,30 @@ cnxk_tim_ring_free(struct rte_event_timer_adapter *adptr) return 0; } +static int +cnxk_tim_stats_get(const struct rte_event_timer_adapter *adapter, + struct rte_event_timer_adapter_stats *stats) +{ + struct cnxk_tim_ring *tim_ring = adapter->data->adapter_priv; + uint64_t bkt_cyc = cnxk_tim_cntvct() - tim_ring->ring_start_cyc; + + stats->evtim_exp_count = + __atomic_load_n(&tim_ring->arm_cnt, __ATOMIC_RELAXED); + stats->ev_enq_count = stats->evtim_exp_count; + stats->adapter_tick_count = + rte_reciprocal_divide_u64(bkt_cyc, &tim_ring->fast_div); + return 0; +} + +static int +cnxk_tim_stats_reset(const struct rte_event_timer_adapter *adapter) +{ + struct cnxk_tim_ring *tim_ring = adapter->data->adapter_priv; + + __atomic_store_n(&tim_ring->arm_cnt, 0, __ATOMIC_RELAXED); + return 0; +} + int cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, uint32_t *caps, @@ -258,6 +287,11 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, cnxk_tim_ops.uninit = cnxk_tim_ring_free; cnxk_tim_ops.get_info = cnxk_tim_ring_info_get; + if (dev->enable_stats) { + cnxk_tim_ops.stats_get = cnxk_tim_stats_get; + cnxk_tim_ops.stats_reset = cnxk_tim_stats_reset; + } + /* Store evdev pointer for later use. */ dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev; *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT; @@ -281,6 +315,8 @@ cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev) &dev->disable_npa); rte_kvargs_process(kvlist, CNXK_TIM_CHNK_SLOTS, &parse_kvargs_value, &dev->chunk_slots); + rte_kvargs_process(kvlist, CNXK_TIM_STATS_ENA, &parse_kvargs_flag, + &dev->enable_stats); rte_kvargs_process(kvlist, CNXK_TIM_RINGS_LMT, &parse_kvargs_value, &dev->min_ring_cnt); diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index 001f448d5..b5e4cfc9e 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -36,12 +36,14 @@ #define CNXK_TIM_DISABLE_NPA "tim_disable_npa" #define CNXK_TIM_CHNK_SLOTS "tim_chnk_slots" +#define CNXK_TIM_STATS_ENA "tim_stats_ena" #define CNXK_TIM_RINGS_LMT "tim_rings_lmt" -#define CNXK_TIM_SP 0x1 -#define CNXK_TIM_MP 0x2 -#define CNXK_TIM_ENA_FB 0x10 -#define CNXK_TIM_ENA_DFB 0x20 +#define CNXK_TIM_SP 0x1 +#define CNXK_TIM_MP 0x2 +#define CNXK_TIM_ENA_FB 0x10 +#define CNXK_TIM_ENA_DFB 0x20 +#define CNXK_TIM_ENA_STATS 0x40 #define TIM_BUCKET_W1_S_CHUNK_REMAINDER (48) #define TIM_BUCKET_W1_M_CHUNK_REMAINDER \ @@ -82,6 +84,7 @@ struct cnxk_tim_evdev { uint8_t disable_npa; uint16_t chunk_slots; uint16_t min_ring_cnt; + uint8_t enable_stats; }; enum cnxk_tim_clk_src { @@ -123,6 +126,7 @@ struct cnxk_tim_ring { struct rte_reciprocal_u64 fast_bkt; uint64_t arm_cnt; uint8_t prod_type_sp; + uint8_t enable_stats; uint8_t disable_npa; uint8_t ena_dfb; uint16_t ring_id; @@ -212,23 +216,33 @@ cnxk_tim_cntfrq(void) #endif #define TIM_ARM_FASTPATH_MODES \ - FP(sp, 0, 0, CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \ - FP(mp, 0, 1, CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \ - FP(fb_sp, 1, 0, CNXK_TIM_ENA_FB | CNXK_TIM_SP) \ - FP(fb_mp, 1, 1, CNXK_TIM_ENA_FB | CNXK_TIM_MP) + FP(sp, 0, 0, 0, CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \ + FP(mp, 0, 0, 1, CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \ + FP(fb_sp, 0, 1, 0, CNXK_TIM_ENA_FB | CNXK_TIM_SP) \ + FP(fb_mp, 0, 1, 1, CNXK_TIM_ENA_FB | CNXK_TIM_MP) \ + FP(stats_sp, 1, 0, 0, \ + CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_DFB | CNXK_TIM_SP) \ + FP(stats_mp, 1, 0, 1, \ + CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_DFB | CNXK_TIM_MP) \ + FP(stats_fb_sp, 1, 1, 0, \ + CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_FB | CNXK_TIM_SP) \ + FP(stats_fb_mp, 1, 1, 1, \ + CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_FB | CNXK_TIM_MP) #define TIM_ARM_TMO_FASTPATH_MODES \ - FP(dfb, 0, CNXK_TIM_ENA_DFB) \ - FP(fb, 1, CNXK_TIM_ENA_FB) + FP(dfb, 0, 0, CNXK_TIM_ENA_DFB) \ + FP(fb, 0, 1, CNXK_TIM_ENA_FB) \ + FP(stats_dfb, 1, 0, CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_DFB) \ + FP(stats_fb, 1, 1, CNXK_TIM_ENA_STATS | CNXK_TIM_ENA_FB) -#define FP(_name, _f2, _f1, flags) \ +#define FP(_name, _f3, _f2, _f1, flags) \ uint16_t cnxk_tim_arm_burst_##_name( \ const struct rte_event_timer_adapter *adptr, \ struct rte_event_timer **tim, const uint16_t nb_timers); TIM_ARM_FASTPATH_MODES #undef FP -#define FP(_name, _f1, flags) \ +#define FP(_name, _f2, _f1, flags) \ uint16_t cnxk_tim_arm_tmo_tick_burst_##_name( \ const struct rte_event_timer_adapter *adptr, \ struct rte_event_timer **tim, const uint64_t timeout_tick, \ diff --git a/drivers/event/cnxk/cnxk_tim_worker.c b/drivers/event/cnxk/cnxk_tim_worker.c index 98ff143c3..3ce99864a 100644 --- a/drivers/event/cnxk/cnxk_tim_worker.c +++ b/drivers/event/cnxk/cnxk_tim_worker.c @@ -86,10 +86,13 @@ cnxk_tim_timer_arm_burst(const struct rte_event_timer_adapter *adptr, } } + if (flags & CNXK_TIM_ENA_STATS) + __atomic_fetch_add(&tim_ring->arm_cnt, index, __ATOMIC_RELAXED); + return index; } -#define FP(_name, _f2, _f1, _flags) \ +#define FP(_name, _f3, _f2, _f1, _flags) \ uint16_t __rte_noinline cnxk_tim_arm_burst_##_name( \ const struct rte_event_timer_adapter *adptr, \ struct rte_event_timer **tim, const uint16_t nb_timers) \ @@ -138,10 +141,14 @@ cnxk_tim_timer_arm_tmo_brst(const struct rte_event_timer_adapter *adptr, break; } + if (flags & CNXK_TIM_ENA_STATS) + __atomic_fetch_add(&tim_ring->arm_cnt, set_timers, + __ATOMIC_RELAXED); + return set_timers; } -#define FP(_name, _f1, _flags) \ +#define FP(_name, _f2, _f1, _flags) \ uint16_t __rte_noinline cnxk_tim_arm_tmo_tick_burst_##_name( \ const struct rte_event_timer_adapter *adptr, \ struct rte_event_timer **tim, const uint64_t timeout_tick, \