From patchwork Tue May 4 00:26:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92680 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6283BA0562; Tue, 4 May 2021 02:28:12 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 319F6410FB; Tue, 4 May 2021 02:28:08 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id DDFF8410FA for ; Tue, 4 May 2021 02:28:06 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1440OuhR025154 for ; Mon, 3 May 2021 17:28:06 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=nJplr7JWkN5D6gTcwW5CW5vjCbqP90uzAxRrSJIA+z4=; b=KjqycTtoQ4Rw7VVZ1dRekBzWCHQ34pIJqAP5MThe6iktNKgRDmnb7jzVVA73NkAW6mDH 5m3ox8VnmkCDaHO/vNTowcMsC4uJObGWY+Z9sknWVtJBxwmms27k+FXpJtRtRV6Os4Ht 3SWMxkDzWTEQMI9/ia8r1xH4vxsdFpD1zgseTtKvHG54eQPQKleTZU+I11A6wCsRvpe/ LY1ffUP/O3jxvXUYm4FgbkJTGB3XSvuvwouii2mW9pgosT/4fTwXfRzrSxgXncc3zNs0 oABQ6oQCQcSS1Eu5tQDgLaipbMqP2JbHDfQY7dTDjO3rc+BzpCjTSuBVYlQxJbc0svQh vA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38agtfjnmt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 17:28:05 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 17:28:04 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 17:28:04 -0700 Received: from BG-LT7430.marvell.com (unknown [10.193.86.144]) by maili.marvell.com (Postfix) with ESMTP id 552C23F7041; Mon, 3 May 2021 17:28:02 -0700 (PDT) From: To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Pavan Nikhilesh Date: Tue, 4 May 2021 05:56:52 +0530 Message-ID: <20210504002726.525-3-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504002726.525-1-pbhagavatula@marvell.com> References: <20210503152238.2437-1-pbhagavatula@marvell.com> <20210504002726.525-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: qYlPYrhqxpdUeMydGq2RRvWngjL1fbRG X-Proofpoint-ORIG-GUID: qYlPYrhqxpdUeMydGq2RRvWngjL1fbRG X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_20:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v5 02/35] common/cnxk: update inline asm prefix X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Update inline asm prefix to prevent overriding cpu type, instead express the additional extensions required. Signed-off-by: Pavan Nikhilesh --- drivers/common/cnxk/roc_platform.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index 29ab71240..7864fa4ff 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -23,9 +23,14 @@ #include "roc_bits.h" #if defined(__ARM_FEATURE_SVE) -#define PLT_CPU_FEATURE_PREAMBLE ".cpu generic+crc+lse+sve\n" +#define PLT_CPU_FEATURE_PREAMBLE \ + ".arch_extension crc\n" \ + ".arch_extension lse\n" \ + ".arch_extension sve\n" #else -#define PLT_CPU_FEATURE_PREAMBLE ".cpu generic+crc+lse\n" +#define PLT_CPU_FEATURE_PREAMBLE \ + ".arch_extension crc\n" \ + ".arch_extension lse\n" #endif #define PLT_ASSERT RTE_ASSERT