From patchwork Mon May 3 15:22:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92641 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6ECBFA0562; Mon, 3 May 2021 17:23:09 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C947F41110; Mon, 3 May 2021 17:23:00 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A64194068C for ; Mon, 3 May 2021 17:22:58 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 143FA9xS032496 for ; Mon, 3 May 2021 08:22:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=2ECxKpzhMfJGae+BunAv7D5vYFYHGE53+esIFAKQnv4=; b=c1oZjGqcQ2GiPHz6XDdh0LfI0SjIeA2mswTm+rKnvHCt8QPENwD7GqZ0ExQqmfZY9B7F RYidG2AQI4iJG9hiM9piHgegL0se/GB9vni4fhDo5YEwZlq5mck9g4s5o8SI4KK+hsjG 7MHKnd7yyG3jATOtNViBcdpptvK1UlVnEErtuvUYgkLR6/j0KfAiUh0MCAcjPr9IWDLB np0WdXcpER6a0IeBNepjT387Rdw++V0wf1v6iRVEBZsQCh62adC0GpN055vz53MwjnMp myKzWnhze9Zqsl2n+fY9QcWRKH1gOxjO9v4Cqy96vNxs5kIkB6+kBLg4Lxcy6VmJh16Y uA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38ad05hedd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 03 May 2021 08:22:58 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 3 May 2021 08:22:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 3 May 2021 08:22:56 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 69AA73F703F; Mon, 3 May 2021 08:22:54 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Mon, 3 May 2021 20:52:06 +0530 Message-ID: <20210503152238.2437-4-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210503152238.2437-1-pbhagavatula@marvell.com> References: <20210430135336.2749-1-pbhagavatula@marvell.com> <20210503152238.2437-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: cT1ysu0kiYkXJJC5rzDbjkUXLA8wvkyM X-Proofpoint-ORIG-GUID: cT1ysu0kiYkXJJC5rzDbjkUXLA8wvkyM X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-03_10:2021-05-03, 2021-05-03 signatures=0 Subject: [dpdk-dev] [PATCH v4 03/34] event/cnxk: add device capabilities function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton Add the info_get function to return details on the queues, flow, prioritization capabilities, etc. which this device has. Signed-off-by: Shijith Thotton Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cnxk_eventdev.c | 24 ++++++++++++++++++++++++ drivers/event/cnxk/cnxk_eventdev.h | 4 ++++ 2 files changed, 28 insertions(+) diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index 7ea782eaa..3a7053af6 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -4,6 +4,30 @@ #include "cnxk_eventdev.h" +void +cnxk_sso_info_get(struct cnxk_sso_evdev *dev, + struct rte_event_dev_info *dev_info) +{ + + dev_info->min_dequeue_timeout_ns = dev->min_dequeue_timeout_ns; + dev_info->max_dequeue_timeout_ns = dev->max_dequeue_timeout_ns; + dev_info->max_event_queues = dev->max_event_queues; + dev_info->max_event_queue_flows = (1ULL << 20); + dev_info->max_event_queue_priority_levels = 8; + dev_info->max_event_priority_levels = 1; + dev_info->max_event_ports = dev->max_event_ports; + dev_info->max_event_port_dequeue_depth = 1; + dev_info->max_event_port_enqueue_depth = 1; + dev_info->max_num_events = dev->max_num_events; + dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_QUEUE_QOS | + RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED | + RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES | + RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK | + RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT | + RTE_EVENT_DEV_CAP_NONSEQ_MODE | + RTE_EVENT_DEV_CAP_CARRY_FLOW_ID; +} + int cnxk_sso_init(struct rte_eventdev *event_dev) { diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 74d0990fa..9745bfd3e 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -17,6 +17,8 @@ struct cnxk_sso_evdev { struct roc_sso sso; + uint8_t max_event_queues; + uint8_t max_event_ports; uint8_t is_timeout_deq; uint8_t nb_event_queues; uint8_t nb_event_ports; @@ -35,5 +37,7 @@ cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev) int cnxk_sso_init(struct rte_eventdev *event_dev); int cnxk_sso_fini(struct rte_eventdev *event_dev); int cnxk_sso_remove(struct rte_pci_device *pci_dev); +void cnxk_sso_info_get(struct cnxk_sso_evdev *dev, + struct rte_event_dev_info *dev_info); #endif /* __CNXK_EVENTDEV_H__ */