From patchwork Fri Apr 30 13:53:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92542 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D2CA8A0546; Fri, 30 Apr 2021 15:57:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3C85F41241; Fri, 30 Apr 2021 15:55:18 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 366764013F for ; Fri, 30 Apr 2021 15:55:17 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 13UDtGnQ022846 for ; Fri, 30 Apr 2021 06:55:16 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=46LXj6+OJw6WuFoSmB0QOL7ZMxoHYX/KJ0zTJo2e7bo=; b=jHfrecCivcb3XPJU6ohqQbCtIpQMTWbKRR/OlobgsukFVXnPW9OZo8BZSUl+An9gymk6 JB4UM8DdMji05/i+ULA279+jv+KDjvX/ofxX5DA2xRm6NHocqs3Da2P/UmAoe7i1uDyy v2PTwdz+GIpdi0UuMbs8unFkkWUFk5Su1ceBIZeGQggYjJrKB3WnVgLW+MhhCzKabLCw 9QVQfpmZri1QqYRcm78acPgY8GVoRN6Pb4825pol1VdnlakHbvnEA9cZ1ZDn/QKEufDb Ngf3U+NoMvQub45b9zNwacyWG9cQqkUdeu9AbKAJfNj65DPmvF2k6dc5fJTRDNCEMTR2 jg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 387rpneaym-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 30 Apr 2021 06:55:16 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 30 Apr 2021 06:55:05 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 30 Apr 2021 06:55:05 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 3EBC13F7050; Fri, 30 Apr 2021 06:55:03 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Fri, 30 Apr 2021 19:23:33 +0530 Message-ID: <20210430135336.2749-31-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430135336.2749-1-pbhagavatula@marvell.com> References: <20210426174441.2302-1-pbhagavatula@marvell.com> <20210430135336.2749-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: hLWHDFYiSEApsPiu49ZUIjkPDWnTsuh6 X-Proofpoint-ORIG-GUID: hLWHDFYiSEApsPiu49ZUIjkPDWnTsuh6 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-30_08:2021-04-30, 2021-04-30 signatures=0 Subject: [dpdk-dev] [PATCH v3 30/33] event/cnxk: add timer cancel function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add function to cancel event timer that has been armed. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- drivers/event/cnxk/cnxk_tim_evdev.c | 1 + drivers/event/cnxk/cnxk_tim_evdev.h | 5 ++++ drivers/event/cnxk/cnxk_tim_worker.c | 30 ++++++++++++++++++++++ drivers/event/cnxk/cnxk_tim_worker.h | 37 ++++++++++++++++++++++++++++ 4 files changed, 73 insertions(+) diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index 68c3b3049..62a15a4a1 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -96,6 +96,7 @@ cnxk_tim_set_fp_ops(struct cnxk_tim_ring *tim_ring) cnxk_tim_ops.arm_burst = arm_burst[tim_ring->ena_dfb][prod_flag]; cnxk_tim_ops.arm_tmo_tick_burst = arm_tmo_burst[tim_ring->ena_dfb]; + cnxk_tim_ops.cancel_burst = cnxk_tim_timer_cancel_burst; } static void diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index b66aac17c..001f448d5 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -236,6 +236,11 @@ TIM_ARM_FASTPATH_MODES TIM_ARM_TMO_FASTPATH_MODES #undef FP +uint16_t +cnxk_tim_timer_cancel_burst(const struct rte_event_timer_adapter *adptr, + struct rte_event_timer **tim, + const uint16_t nb_timers); + int cnxk_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags, uint32_t *caps, const struct rte_event_timer_adapter_ops **ops); diff --git a/drivers/event/cnxk/cnxk_tim_worker.c b/drivers/event/cnxk/cnxk_tim_worker.c index 717c53fb7..98ff143c3 100644 --- a/drivers/event/cnxk/cnxk_tim_worker.c +++ b/drivers/event/cnxk/cnxk_tim_worker.c @@ -152,3 +152,33 @@ cnxk_tim_timer_arm_tmo_brst(const struct rte_event_timer_adapter *adptr, } TIM_ARM_TMO_FASTPATH_MODES #undef FP + +uint16_t +cnxk_tim_timer_cancel_burst(const struct rte_event_timer_adapter *adptr, + struct rte_event_timer **tim, + const uint16_t nb_timers) +{ + uint16_t index; + int ret; + + RTE_SET_USED(adptr); + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); + for (index = 0; index < nb_timers; index++) { + if (tim[index]->state == RTE_EVENT_TIMER_CANCELED) { + rte_errno = EALREADY; + break; + } + + if (tim[index]->state != RTE_EVENT_TIMER_ARMED) { + rte_errno = EINVAL; + break; + } + ret = cnxk_tim_rm_entry(tim[index]); + if (ret) { + rte_errno = -ret; + break; + } + } + + return index; +} diff --git a/drivers/event/cnxk/cnxk_tim_worker.h b/drivers/event/cnxk/cnxk_tim_worker.h index 56cb4cdd9..7caeb1a8f 100644 --- a/drivers/event/cnxk/cnxk_tim_worker.h +++ b/drivers/event/cnxk/cnxk_tim_worker.h @@ -561,4 +561,41 @@ cnxk_tim_add_entry_brst(struct cnxk_tim_ring *const tim_ring, return nb_timers; } +static int +cnxk_tim_rm_entry(struct rte_event_timer *tim) +{ + struct cnxk_tim_ent *entry; + struct cnxk_tim_bkt *bkt; + uint64_t lock_sema; + + if (tim->impl_opaque[1] == 0 || tim->impl_opaque[0] == 0) + return -ENOENT; + + entry = (struct cnxk_tim_ent *)(uintptr_t)tim->impl_opaque[0]; + if (entry->wqe != tim->ev.u64) { + tim->impl_opaque[0] = 0; + tim->impl_opaque[1] = 0; + return -ENOENT; + } + + bkt = (struct cnxk_tim_bkt *)(uintptr_t)tim->impl_opaque[1]; + lock_sema = cnxk_tim_bkt_inc_lock(bkt); + if (cnxk_tim_bkt_get_hbt(lock_sema) || + !cnxk_tim_bkt_get_nent(lock_sema)) { + tim->impl_opaque[0] = 0; + tim->impl_opaque[1] = 0; + cnxk_tim_bkt_dec_lock(bkt); + return -ENOENT; + } + + entry->w0 = 0; + entry->wqe = 0; + tim->state = RTE_EVENT_TIMER_CANCELED; + tim->impl_opaque[0] = 0; + tim->impl_opaque[1] = 0; + cnxk_tim_bkt_dec_lock(bkt); + + return 0; +} + #endif /* __CNXK_TIM_WORKER_H__ */