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[89.79.189.199]) by smtp.gmail.com with ESMTPSA id l13sm13476245wmj.3.2021.04.30.05.58.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Apr 2021 05:58:04 -0700 (PDT) From: Michal Krawczyk To: dev@dpdk.org Cc: ndagan@amazom.com, gtzalik@amazon.com, igorch@amazon.com, mw@semihalf.com, Stanislaw Kardach , stable@dpdk.org, Michal Krawczyk , Shay Agroskin Date: Fri, 30 Apr 2021 14:57:24 +0200 Message-Id: <20210430125725.28796-22-mk@semihalf.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210430125725.28796-1-mk@semihalf.com> References: <20210430125725.28796-1-mk@semihalf.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 21/22] net/ena: report default ring size X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Stanislaw Kardach Remove invalid ring size alignment logic and add default rx and tx port ring sizes to the device info spec. The logic in lines 1297 and 1371 is invalid. The RTE_ETH_DEV_FALLBACK_RX_RINGSIZE (and the TX counterpart) is a value that rte_eth_rx_queue_setup() will set if dev_info.default_rxportconf.ring_size is 0 and user provided 0 in nb_rx_desc argument. However the current code treats it as a hint for the PMD to change the ring size to internal defaults. Additionally since the ENA_DEFAULT_RING_SIZE is defined, report it in the device capabilities so that both rte_ethdev code and the user can utilize it for device configuration. Fixes: ea93d37eb49d ("net/ena: add HW queues depth setup") Cc: stable@dpdk.org Signed-off-by: Stanislaw Kardach Reviewed-by: Michal Krawczyk Reviewed-by: Igor Chauskin Reviewed-by: Shay Agroskin --- drivers/net/ena/ena_ethdev.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index 73e99e956a..c5d8e7d43e 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -1294,9 +1294,6 @@ static int ena_tx_queue_setup(struct rte_eth_dev *dev, return -EINVAL; } - if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE) - nb_desc = adapter->max_tx_ring_size; - txq->port_id = dev->data->port_id; txq->next_to_clean = 0; txq->next_to_use = 0; @@ -1368,9 +1365,6 @@ static int ena_rx_queue_setup(struct rte_eth_dev *dev, return ENA_COM_FAULT; } - if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE) - nb_desc = adapter->max_rx_ring_size; - if (!rte_is_power_of_2(nb_desc)) { PMD_DRV_LOG(ERR, "Unsupported size of RX queue: %d is not a power of 2.\n", @@ -2130,6 +2124,9 @@ static int ena_infos_get(struct rte_eth_dev *dev, dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, adapter->max_tx_sgl_size); + dev_info->default_rxportconf.ring_size = ENA_DEFAULT_RING_SIZE; + dev_info->default_txportconf.ring_size = ENA_DEFAULT_RING_SIZE; + return 0; }