From patchwork Mon Apr 26 17:44:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 92194 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 42027A0548; Mon, 26 Apr 2021 19:45:58 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7E13741216; Mon, 26 Apr 2021 19:45:23 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 9DA3141200 for ; Mon, 26 Apr 2021 19:45:22 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 13QHis2t030120 for ; Mon, 26 Apr 2021 10:45:22 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=gf/iHZvgxfWEhSNtyXSBrpEeclvFmHe6Nwzv2fZoK3c=; b=c9W8nxRvwBmFnGGmxhm0h7lsLVFWvkXs+76u45JaT4VTGPo5YanIVvodd+SZfCXGAcxU FCI4HBJOwk+bI9fACKd4kXvMlIrHGirGgDgiv6rR0N/zd1v9Wu/1RuCl6+5H1OY/1Erv 8uPJLAdGiY7mFPtUeboO0wvot+X/I6X1jupe4az44+c8TU4dKHnBe2qxjBKh6fecsYB0 RB/yrma1oFWDZ3ui2o1HO6lClLGmULvuCpIFzC+n/PXfCnYt1uL4jLZV6c4Ye4YIJ2g1 LRCODLBWLI+9pIa7cKU6UZ0DFL2BbD1TxvPGjIAT1z2skAn2pkpJLPvV6vSNfY+VxADq IA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 385tvvhde0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 26 Apr 2021 10:45:22 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 26 Apr 2021 10:45:20 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 26 Apr 2021 10:45:20 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 2DE0B5B6C96; Mon, 26 Apr 2021 10:45:17 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Date: Mon, 26 Apr 2021 23:14:15 +0530 Message-ID: <20210426174441.2302-9-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210426174441.2302-1-pbhagavatula@marvell.com> References: <20210306162942.6845-1-pbhagavatula@marvell.com> <20210426174441.2302-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: Z_xxedzXLGzrDhKpkml5ePefQE8kybvG X-Proofpoint-ORIG-GUID: Z_xxedzXLGzrDhKpkml5ePefQE8kybvG X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-26_09:2021-04-26, 2021-04-26 signatures=0 Subject: [dpdk-dev] [PATCH v2 08/33] event/cnxk: add devargs for inflight buffer count X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Shijith Thotton The number of events for a *open system* event device is specified as -1 as per the eventdev specification. Since, SSO inflight events are only limited by DRAM size, the xae_cnt devargs parameter is introduced to provide upper limit for in-flight events. Example: --dev "0002:0e:00.0,xae_cnt=8192" Signed-off-by: Shijith Thotton Signed-off-by: Pavan Nikhilesh --- doc/guides/eventdevs/cnxk.rst | 14 ++++++++++++++ drivers/event/cnxk/cn10k_eventdev.c | 1 + drivers/event/cnxk/cn9k_eventdev.c | 1 + drivers/event/cnxk/cnxk_eventdev.c | 24 ++++++++++++++++++++++-- drivers/event/cnxk/cnxk_eventdev.h | 15 +++++++++++++++ 5 files changed, 53 insertions(+), 2 deletions(-) diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst index e94225bd3..569fce4cb 100644 --- a/doc/guides/eventdevs/cnxk.rst +++ b/doc/guides/eventdevs/cnxk.rst @@ -41,6 +41,20 @@ Prerequisites and Compilation procedure See :doc:`../platform/cnxk` for setup information. + +Runtime Config Options +---------------------- + +- ``Maximum number of in-flight events`` (default ``8192``) + + In **Marvell OCTEON CNXK** the max number of in-flight events are only limited + by DRAM size, the ``xae_cnt`` devargs parameter is introduced to provide + upper limit for in-flight events. + + For example:: + + -a 0002:0e:00.0,xae_cnt=16384 + Debugging Options ----------------- diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 7e3fa20c5..1b278360f 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -143,3 +143,4 @@ static struct rte_pci_driver cn10k_pci_sso = { RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso); RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "="); diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 71245b660..8dfcf35b4 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -146,3 +146,4 @@ static struct rte_pci_driver cn9k_pci_sso = { RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso); RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci"); +RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "="); diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index 927f99117..28a03aeab 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -75,8 +75,11 @@ cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev) /* Taken from HRM 14.3.3(4) */ xaq_cnt = dev->nb_event_queues * CNXK_SSO_XAQ_CACHE_CNT; - xaq_cnt += (dev->sso.iue / dev->sso.xae_waes) + - (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues); + if (dev->xae_cnt) + xaq_cnt += dev->xae_cnt / dev->sso.xae_waes; + else + xaq_cnt += (dev->sso.iue / dev->sso.xae_waes) + + (CNXK_SSO_XAQ_SLACK * dev->nb_event_queues); plt_sso_dbg("Configuring %d xaq buffers", xaq_cnt); /* Setup XAQ based on number of nb queues. */ @@ -222,6 +225,22 @@ cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id, port_conf->enqueue_depth = 1; } +static void +cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs) +{ + struct rte_kvargs *kvlist; + + if (devargs == NULL) + return; + kvlist = rte_kvargs_parse(devargs->args, NULL); + if (kvlist == NULL) + return; + + rte_kvargs_process(kvlist, CNXK_SSO_XAE_CNT, &parse_kvargs_value, + &dev->xae_cnt); + rte_kvargs_free(kvlist); +} + int cnxk_sso_init(struct rte_eventdev *event_dev) { @@ -242,6 +261,7 @@ cnxk_sso_init(struct rte_eventdev *event_dev) dev->sso.pci_dev = pci_dev; *(uint64_t *)mz->addr = (uint64_t)dev; + cnxk_sso_parse_devargs(dev, pci_dev->device.devargs); /* Initialize the base cnxk_dev object */ rc = roc_sso_dev_init(&dev->sso); diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 8478120c0..72b0ff3f8 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -5,6 +5,8 @@ #ifndef __CNXK_EVENTDEV_H__ #define __CNXK_EVENTDEV_H__ +#include +#include #include #include @@ -12,6 +14,8 @@ #include "roc_api.h" +#define CNXK_SSO_XAE_CNT "xae_cnt" + #define USEC2NSEC(__us) ((__us)*1E3) #define CNXK_SSO_FC_NAME "cnxk_evdev_xaq_fc" @@ -35,10 +39,21 @@ struct cnxk_sso_evdev { uint64_t nb_xaq_cfg; rte_iova_t fc_iova; struct rte_mempool *xaq_pool; + /* Dev args */ + uint32_t xae_cnt; /* CN9K */ uint8_t dual_ws; } __rte_cache_aligned; +static inline int +parse_kvargs_value(const char *key, const char *value, void *opaque) +{ + RTE_SET_USED(key); + + *(uint32_t *)opaque = (uint32_t)atoi(value); + return 0; +} + static inline struct cnxk_sso_evdev * cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev) {