From patchwork Fri Apr 23 11:40:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Haiyue" X-Patchwork-Id: 92081 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 08FF9A0548; Fri, 23 Apr 2021 14:06:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9A33641DFC; Fri, 23 Apr 2021 14:06:19 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id ABFDD41DF3 for ; Fri, 23 Apr 2021 14:06:15 +0200 (CEST) IronPort-SDR: Q8jlESCxKm4hkUoKoA/ZPeZp3St769XMuhauwKkUCzWd2Pz5YHVbHqDbPUye5GM67V+blMkNwR f7XlovdQMG3A== X-IronPort-AV: E=McAfee;i="6200,9189,9962"; a="183538021" X-IronPort-AV: E=Sophos;i="5.82,245,1613462400"; d="scan'208";a="183538021" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2021 05:06:15 -0700 IronPort-SDR: 42Z50DFhK0Au675a84zWVhubbtZPylagksgZGz29uSAnsHAfQ23QjwtiWI/CyNKCfvirgG1LpH ZzLGEZMFQrOg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,245,1613462400"; d="scan'208";a="428359991" Received: from npg-dpdk-haiyue-2.sh.intel.com ([10.67.119.63]) by orsmga008.jf.intel.com with ESMTP; 23 Apr 2021 05:06:13 -0700 From: Haiyue Wang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, liang-min.wang@intel.com, Haiyue Wang , Beilei Xing , Jeff Guo Date: Fri, 23 Apr 2021 19:40:01 +0800 Message-Id: <20210423114001.174723-4-haiyue.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210423114001.174723-1-haiyue.wang@intel.com> References: <20210421050243.130585-1-haiyue.wang@intel.com> <20210423114001.174723-1-haiyue.wang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 3/3] net/i40e: enable PCI bus master after reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The VF reset can be triggerred by the PF reset event, in this case, the PCI bus master will be cleared, then the VF is not allowed to issue any Memory or I/O Requests. So after the reset event is detected, always enable the PCI bus master. And align the VF reset event handling in device close module as the AVF driver does. Signed-off-by: Haiyue Wang Tested-by: Qi Zhang --- drivers/net/i40e/i40e_ethdev_vf.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c index 3c258ba7c..4f1d04eb2 100644 --- a/drivers/net/i40e/i40e_ethdev_vf.c +++ b/drivers/net/i40e/i40e_ethdev_vf.c @@ -1212,7 +1212,6 @@ i40evf_check_vf_reset_done(struct rte_eth_dev *dev) if (i >= MAX_RESET_WAIT_CNT) return -1; - vf->vf_reset = false; vf->pend_msg &= ~PFMSG_RESET_IMPENDING; return 0; @@ -1391,6 +1390,7 @@ i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg, switch (pf_msg->event) { case VIRTCHNL_EVENT_RESET_IMPENDING: PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event"); + vf->vf_reset = true; rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL); break; @@ -2487,6 +2487,11 @@ i40evf_dev_close(struct rte_eth_dev *dev) i40e_shutdown_adminq(hw); i40evf_disable_irq0(hw); + if (vf->vf_reset) + rte_pci_enable_bus_master(RTE_ETH_DEV_TO_PCI(dev)); + + vf->vf_reset = false; + rte_free(vf->vf_res); vf->vf_res = NULL; rte_free(vf->aq_resp);