From patchwork Fri Apr 23 11:40:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Haiyue" X-Patchwork-Id: 92080 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C1C3BA0548; Fri, 23 Apr 2021 14:06:24 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6FF6341DF6; Fri, 23 Apr 2021 14:06:18 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id B787741DEA for ; Fri, 23 Apr 2021 14:06:14 +0200 (CEST) IronPort-SDR: 97ZAutjE4TGCtTU6sm5gb01PBghqelyrBQVkhMsnSPyeFRY5um5wD/c2aCWqoUnRDGjwiupJuQ WbEqMBUM9ukQ== X-IronPort-AV: E=McAfee;i="6200,9189,9962"; a="183538015" X-IronPort-AV: E=Sophos;i="5.82,245,1613462400"; d="scan'208";a="183538015" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Apr 2021 05:06:14 -0700 IronPort-SDR: wgBj5DGmOM79i7lgmak/ijAGwVkydZqc0zMo9/xQuWA7kvbI4HlbOR8LdbyGg6W8uvgnSvJsWq 6huZhDX+J/mQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,245,1613462400"; d="scan'208";a="428359975" Received: from npg-dpdk-haiyue-2.sh.intel.com ([10.67.119.63]) by orsmga008.jf.intel.com with ESMTP; 23 Apr 2021 05:06:11 -0700 From: Haiyue Wang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, liang-min.wang@intel.com, Haiyue Wang , Jingjing Wu , Beilei Xing Date: Fri, 23 Apr 2021 19:40:00 +0800 Message-Id: <20210423114001.174723-3-haiyue.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210423114001.174723-1-haiyue.wang@intel.com> References: <20210421050243.130585-1-haiyue.wang@intel.com> <20210423114001.174723-1-haiyue.wang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 2/3] net/iavf: enable PCI bus master after reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The VF reset can be triggerred by the PF reset event, in this case, the PCI bus master will be cleared, then the VF is not allowed to issue any Memory or I/O Requests. So after the reset event is detected, always enable the PCI bus master. Signed-off-by: Haiyue Wang Tested-by: Qi Zhang --- drivers/net/iavf/iavf_ethdev.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c index d523a0618..8c924d21b 100644 --- a/drivers/net/iavf/iavf_ethdev.c +++ b/drivers/net/iavf/iavf_ethdev.c @@ -2255,6 +2255,9 @@ iavf_dev_close(struct rte_eth_dev *dev) rte_free(vf->aq_resp); vf->aq_resp = NULL; + if (vf->vf_reset) + rte_pci_enable_bus_master(pci_dev); + vf->vf_reset = false; return ret;