| Message ID | 20210422072446.29455-1-xuemingl@nvidia.com (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Delegated to: | Raslan Darawsheh |
| Headers | show |
| Series | net/mlx5: probe LAG representor with PF1 PCI address | expand |
| Context | Check | Description |
|---|---|---|
| ci/iol-mellanox-Performance | success | Performance Testing PASS |
| ci/iol-intel-Performance | success | Performance Testing PASS |
| ci/iol-abi-testing | success | Testing PASS |
| ci/iol-testing | success | Testing PASS |
| ci/intel-Testing | success | Testing PASS |
| ci/Intel-compilation | success | Compilation OK |
| ci/github-robot | success | github build: passed |
| ci/checkpatch | success | coding style OK |
Hi, Xuemig This patch looks like a fix - could you, please add the "Fixes:" tag and modify the headline? With best regards, Slava > -----Original Message----- > From: Xueming Li <xuemingl@nvidia.com> > Sent: Thursday, April 22, 2021 10:25 > Cc: dev@dpdk.org; Xueming(Steven) Li <xuemingl@nvidia.com>; Matan > Azrad <matan@nvidia.com>; Shahaf Shuler <shahafs@nvidia.com>; Slava > Ovsiienko <viacheslavo@nvidia.com> > Subject: [PATCH] net/mlx5: probe LAG representor with PF1 PCI address > > In case of bonding, orchestrator wants to use same devargs for LAG and non- > LAG scenario, to probe representor on PF1 using PF1 PCI address like > "<DBDF_PF1>,representor=pf1vf[0-3]". > > This patch changes PCI address check policy to allow PF1 PCI address for > representors on PF1. > > Note: detaching PF0 device can't remove representors on PF1. It's > recommended to use primary(PF0) PCI address to probe representors on > both PFs. > > Signed-off-by: Xueming Li <xuemingl@nvidia.com> > --- > drivers/net/mlx5/linux/mlx5_os.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/mlx5/linux/mlx5_os.c > b/drivers/net/mlx5/linux/mlx5_os.c > index 76c72d0e38..22271e289a 100644 > --- a/drivers/net/mlx5/linux/mlx5_os.c > +++ b/drivers/net/mlx5/linux/mlx5_os.c > @@ -1875,11 +1875,14 @@ mlx5_device_bond_pci_match(const struct > ibv_device *ibv_dev, > tmp_str); > break; > } > - /* Match PCI address. */ > + /* Match PCI address, allows BDF0+pfx or BDFx+pfx. */ > if (pci_dev->domain == pci_addr.domain && > pci_dev->bus == pci_addr.bus && > pci_dev->devid == pci_addr.devid && > - pci_dev->function + owner == pci_addr.function) > + ((pci_dev->function == 0 && > + pci_dev->function + owner == pci_addr.function) || > + (pci_dev->function == owner && > + pci_addr.function == owner))) > pf = info.port_name; > /* Get ifindex. */ > snprintf(tmp_str, sizeof(tmp_str), > -- > 2.25.1
diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index 76c72d0e38..22271e289a 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1875,11 +1875,14 @@ mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, tmp_str); break; } - /* Match PCI address. */ + /* Match PCI address, allows BDF0+pfx or BDFx+pfx. */ if (pci_dev->domain == pci_addr.domain && pci_dev->bus == pci_addr.bus && pci_dev->devid == pci_addr.devid && - pci_dev->function + owner == pci_addr.function) + ((pci_dev->function == 0 && + pci_dev->function + owner == pci_addr.function) || + (pci_dev->function == owner && + pci_addr.function == owner))) pf = info.port_name; /* Get ifindex. */ snprintf(tmp_str, sizeof(tmp_str),
In case of bonding, orchestrator wants to use same devargs for LAG and non-LAG scenario, to probe representor on PF1 using PF1 PCI address like "<DBDF_PF1>,representor=pf1vf[0-3]". This patch changes PCI address check policy to allow PF1 PCI address for representors on PF1. Note: detaching PF0 device can't remove representors on PF1. It's recommended to use primary(PF0) PCI address to probe representors on both PFs. Signed-off-by: Xueming Li <xuemingl@nvidia.com> --- drivers/net/mlx5/linux/mlx5_os.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)