From patchwork Thu Apr 22 01:18:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Haiyue" X-Patchwork-Id: 91980 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 619B2A0547; Thu, 22 Apr 2021 03:38:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 799D841C21; Thu, 22 Apr 2021 03:38:07 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id B6FF941C18 for ; Thu, 22 Apr 2021 03:38:03 +0200 (CEST) IronPort-SDR: sM0VSxdmUz61lW2y/3kGyvcKJN3kcO05Tyi4+YSeJ5YuU+tPBr0RYsl8oWsY4yLA1GLrezRQ8Q UdtYEYwOyCEg== X-IronPort-AV: E=McAfee;i="6200,9189,9961"; a="193689958" X-IronPort-AV: E=Sophos;i="5.82,241,1613462400"; d="scan'208";a="193689958" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2021 18:38:03 -0700 IronPort-SDR: PIDyViECMXnno0rgkc+5MD7bmG+cjtL+kRUD36rLPhKNjmlZPPq2KqbjbZTGiY6tqJEBVQs7lp 4prY//1eB6+g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,241,1613462400"; d="scan'208";a="401672467" Received: from npg-dpdk-haiyue-1.sh.intel.com ([10.67.118.220]) by orsmga002.jf.intel.com with ESMTP; 21 Apr 2021 18:38:01 -0700 From: Haiyue Wang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, liang-min.wang@intel.com, Haiyue Wang , Beilei Xing , Jeff Guo Date: Thu, 22 Apr 2021 09:18:30 +0800 Message-Id: <20210422011830.54199-4-haiyue.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210422011830.54199-1-haiyue.wang@intel.com> References: <20210421050243.130585-1-haiyue.wang@intel.com> <20210422011830.54199-1-haiyue.wang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 3/3] net/i40e: enable PCI bus master after reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The VF reset can be triggerred by the PF reset event, in this case, the PCI bus master will be cleared, then the VF is not allowed to issue any Memory or I/O Requests. So after the reset event is detected, always enable the PCI bus master. And align the VF reset event handling in device close module as the AVF driver does. Signed-off-by: Haiyue Wang Tested-by: Qi Zhang --- drivers/net/i40e/i40e_ethdev_vf.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/i40e/i40e_ethdev_vf.c b/drivers/net/i40e/i40e_ethdev_vf.c index 3c258ba7c..4f1d04eb2 100644 --- a/drivers/net/i40e/i40e_ethdev_vf.c +++ b/drivers/net/i40e/i40e_ethdev_vf.c @@ -1212,7 +1212,6 @@ i40evf_check_vf_reset_done(struct rte_eth_dev *dev) if (i >= MAX_RESET_WAIT_CNT) return -1; - vf->vf_reset = false; vf->pend_msg &= ~PFMSG_RESET_IMPENDING; return 0; @@ -1391,6 +1390,7 @@ i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg, switch (pf_msg->event) { case VIRTCHNL_EVENT_RESET_IMPENDING: PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event"); + vf->vf_reset = true; rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL); break; @@ -2487,6 +2487,11 @@ i40evf_dev_close(struct rte_eth_dev *dev) i40e_shutdown_adminq(hw); i40evf_disable_irq0(hw); + if (vf->vf_reset) + rte_pci_enable_bus_master(RTE_ETH_DEV_TO_PCI(dev)); + + vf->vf_reset = false; + rte_free(vf->vf_res); vf->vf_res = NULL; rte_free(vf->aq_resp);