From patchwork Thu Apr 22 01:18:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Haiyue" X-Patchwork-Id: 91979 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C28C9A0547; Thu, 22 Apr 2021 03:38:11 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4187841C1A; Thu, 22 Apr 2021 03:38:04 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id B81C041C13 for ; Thu, 22 Apr 2021 03:38:01 +0200 (CEST) IronPort-SDR: Kg4ZqawtT+ZfkACm+HPe6IZirp0VZjKZXKo7kQbGkbBm9A/IIveArKnEBp6nqYoS/+1ZFWmCWA PWox31LtjlTw== X-IronPort-AV: E=McAfee;i="6200,9189,9961"; a="193689955" X-IronPort-AV: E=Sophos;i="5.82,241,1613462400"; d="scan'208";a="193689955" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2021 18:38:01 -0700 IronPort-SDR: f4x8TYXvjoMN+sKlBZ3Qy6UTz/0ON3Cq78ZaOfh1vpKRkpvBhIr+/r3O4JVAPkRB6KsOHDX3/u E7GhEPgDu3bg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,241,1613462400"; d="scan'208";a="401672456" Received: from npg-dpdk-haiyue-1.sh.intel.com ([10.67.118.220]) by orsmga002.jf.intel.com with ESMTP; 21 Apr 2021 18:37:59 -0700 From: Haiyue Wang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, liang-min.wang@intel.com, Haiyue Wang , Jingjing Wu , Beilei Xing Date: Thu, 22 Apr 2021 09:18:29 +0800 Message-Id: <20210422011830.54199-3-haiyue.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210422011830.54199-1-haiyue.wang@intel.com> References: <20210421050243.130585-1-haiyue.wang@intel.com> <20210422011830.54199-1-haiyue.wang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 2/3] net/iavf: enable PCI bus master after reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The VF reset can be triggerred by the PF reset event, in this case, the PCI bus master will be cleared, then the VF is not allowed to issue any Memory or I/O Requests. So after the reset event is detected, always enable the PCI bus master. Signed-off-by: Haiyue Wang Tested-by: Qi Zhang --- drivers/net/iavf/iavf_ethdev.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c index d523a0618..8c924d21b 100644 --- a/drivers/net/iavf/iavf_ethdev.c +++ b/drivers/net/iavf/iavf_ethdev.c @@ -2255,6 +2255,9 @@ iavf_dev_close(struct rte_eth_dev *dev) rte_free(vf->aq_resp); vf->aq_resp = NULL; + if (vf->vf_reset) + rte_pci_enable_bus_master(pci_dev); + vf->vf_reset = false; return ret;