From patchwork Wed Apr 21 05:02:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Haiyue" X-Patchwork-Id: 91917 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ED69EA0548; Wed, 21 Apr 2021 07:22:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CC97D41943; Wed, 21 Apr 2021 07:22:42 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id 45C514193B for ; Wed, 21 Apr 2021 07:22:40 +0200 (CEST) IronPort-SDR: vVgfgeiNb1jTx5RKMwrSCi0G0zxffTn7Tst0fdeCpdJeUU9EJwufrIDbEcgSeWEY9bdwAs3MWV 4ml8bfu7Qs+w== X-IronPort-AV: E=McAfee;i="6200,9189,9960"; a="195197399" X-IronPort-AV: E=Sophos;i="5.82,238,1613462400"; d="scan'208";a="195197399" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Apr 2021 22:22:39 -0700 IronPort-SDR: nntgTU+dBeTwrU95lspt+OfLGhpzYQxdbHcTOViqYPnPmy9G9NSl9cUDPWQLPezCzcJtq1cisG B6q8L9aUSEIQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,238,1613462400"; d="scan'208";a="427380655" Received: from npg-dpdk-haiyue-1.sh.intel.com ([10.67.118.220]) by orsmga008.jf.intel.com with ESMTP; 20 Apr 2021 22:22:38 -0700 From: Haiyue Wang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, liang-min.wang@intel.com, Haiyue Wang , Jingjing Wu , Beilei Xing Date: Wed, 21 Apr 2021 13:02:42 +0800 Message-Id: <20210421050243.130585-3-haiyue.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210421050243.130585-1-haiyue.wang@intel.com> References: <20210421050243.130585-1-haiyue.wang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v1 2/3] net/iavf: enable PCI bus master after reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The VF reset can be triggerred by the PF reset event, in this case, the PCI bus master will be cleared, then the VF is not allowed to issue any Memory or I/O Requests. So after the reset event is detected, always enable the PCI bus master. Signed-off-by: Haiyue Wang --- drivers/net/iavf/iavf_ethdev.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c index d523a0618c..8c924d21b2 100644 --- a/drivers/net/iavf/iavf_ethdev.c +++ b/drivers/net/iavf/iavf_ethdev.c @@ -2255,6 +2255,9 @@ iavf_dev_close(struct rte_eth_dev *dev) rte_free(vf->aq_resp); vf->aq_resp = NULL; + if (vf->vf_reset) + rte_pci_enable_bus_master(pci_dev); + vf->vf_reset = false; return ret;