diff mbox series

[v2] net/i40e: fix FDIR issue for common PCTYPEs

Message ID 20210421020830.4989-1-murphyx.yang@intel.com (mailing list archive)
State Superseded
Delegated to: Qi Zhang
Headers show
Series [v2] net/i40e: fix FDIR issue for common PCTYPEs | expand

Checks

Context Check Description
ci/intel-Testing success Testing PASS
ci/Intel-compilation success Compilation OK
ci/github-robot success github build: passed
ci/travis-robot success travis build: passed
ci/checkpatch success coding style OK

Commit Message

Murphy Yang April 21, 2021, 2:08 a.m. UTC
Currently, FDIR doesn't work for all common PCTYPEs, the root cause is
that input set is not configured.

Fixes: 4a072ad43442 ("net/i40e: fix flow director config after flow validate")
Signed-off-by: Murphy Yang <murphyx.yang@intel.com>
---
v2:
- tune the code and modify commit message
 drivers/net/i40e/i40e_fdir.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

Comments

Xing, Beilei April 21, 2021, 3:25 a.m. UTC | #1
> -----Original Message-----
> From: Yang, MurphyX <murphyx.yang@intel.com>
> Sent: Wednesday, April 21, 2021 10:09 AM
> To: dev@dpdk.org
> Cc: Yang, Qiming <qiming.yang@intel.com>; Guo, Jia <jia.guo@intel.com>;
> Xing, Beilei <beilei.xing@intel.com>; Yang, SteveX <stevex.yang@intel.com>;
> Zhang, RobinX <robinx.zhang@intel.com>; Yang, MurphyX
> <murphyx.yang@intel.com>
> Subject: [PATCH v2] net/i40e: fix FDIR issue for common PCTYPEs
> 
> Currently, FDIR doesn't work for all common PCTYPEs, the root cause is that
> input set is not configured.
> 
> Fixes: 4a072ad43442 ("net/i40e: fix flow director config after flow validate")
> Signed-off-by: Murphy Yang <murphyx.yang@intel.com>
> ---
> v2:
> - tune the code and modify commit message  drivers/net/i40e/i40e_fdir.c | 13
> +++++++++----
>  1 file changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c index
> da089baa4d..6b81e09db5 100644
> --- a/drivers/net/i40e/i40e_fdir.c
> +++ b/drivers/net/i40e/i40e_fdir.c
> @@ -1607,8 +1607,10 @@ i40e_flow_set_fdir_inset(struct i40e_pf *pf,
> 
>  	/* Check if the configuration is conflicted */
>  	if (pf->fdir.inset_flag[pctype] &&
> -	    memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
> -		return -1;
> +	    memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
> {
> +		PMD_DRV_LOG(ERR, "Conflict with the first rule's input set.");
> +		return -EINVAL;
> +	}
> 
>  	if (pf->fdir.inset_flag[pctype] &&
>  	    !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
> @@ -1762,18 +1764,21 @@ i40e_flow_add_del_fdir_filter(struct rte_eth_dev
> *dev,
>  	i40e_fdir_filter_convert(filter, &check_filter);
> 
>  	if (add) {
> -		if (filter->input.flow_ext.is_flex_flow) {
> +		/* configure the input set for common PCTYPEs*/
> +		if (!filter->input.flow_ext.customized_pctype) {
>  			ret = i40e_flow_set_fdir_inset(pf, pctype,
>  					filter->input.flow_ext.input_set);
>  			if (ret == -1) {
>  				PMD_DRV_LOG(ERR, "Conflict with the"
> -					    " first rule's input set.");
> +						    " first rule's input set.");

The log is duplicated with above.

>  				return -EINVAL;
>  			} else if (ret == -EINVAL) {
>  				PMD_DRV_LOG(ERR, "Invalid pattern mask.");
>  				return -EINVAL;
>  			}
> +		}
> 
> +		if (filter->input.flow_ext.is_flex_flow) {
>  			for (i = 0; i < filter->input.flow_ext.raw_id; i++) {
>  				layer_idx = filter->input.flow_ext.layer_idx;
>  				field_idx = layer_idx * I40E_MAX_FLXPLD_FIED
> + i;
> --
> 2.17.1
diff mbox series

Patch

diff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c
index da089baa4d..6b81e09db5 100644
--- a/drivers/net/i40e/i40e_fdir.c
+++ b/drivers/net/i40e/i40e_fdir.c
@@ -1607,8 +1607,10 @@  i40e_flow_set_fdir_inset(struct i40e_pf *pf,
 
 	/* Check if the configuration is conflicted */
 	if (pf->fdir.inset_flag[pctype] &&
-	    memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
-		return -1;
+	    memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t))) {
+		PMD_DRV_LOG(ERR, "Conflict with the first rule's input set.");
+		return -EINVAL;
+	}
 
 	if (pf->fdir.inset_flag[pctype] &&
 	    !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
@@ -1762,18 +1764,21 @@  i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
 	i40e_fdir_filter_convert(filter, &check_filter);
 
 	if (add) {
-		if (filter->input.flow_ext.is_flex_flow) {
+		/* configure the input set for common PCTYPEs*/
+		if (!filter->input.flow_ext.customized_pctype) {
 			ret = i40e_flow_set_fdir_inset(pf, pctype,
 					filter->input.flow_ext.input_set);
 			if (ret == -1) {
 				PMD_DRV_LOG(ERR, "Conflict with the"
-					    " first rule's input set.");
+						    " first rule's input set.");
 				return -EINVAL;
 			} else if (ret == -EINVAL) {
 				PMD_DRV_LOG(ERR, "Invalid pattern mask.");
 				return -EINVAL;
 			}
+		}
 
+		if (filter->input.flow_ext.is_flex_flow) {
 			for (i = 0; i < filter->input.flow_ext.raw_id; i++) {
 				layer_idx = filter->input.flow_ext.layer_idx;
 				field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;