From patchwork Tue Apr 20 02:05:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alvin Zhang X-Patchwork-Id: 91805 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 29D92A0524; Tue, 20 Apr 2021 04:05:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1328441583; Tue, 20 Apr 2021 04:05:32 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id B515A40688; Tue, 20 Apr 2021 04:05:29 +0200 (CEST) IronPort-SDR: lyvSGZn+uomoJ9OiPfACgPH//Tci69ZxOYFwK5Vd4ohYo5arldHCnDqggF8zGE6MhwN63EWNrc O7WFodF50PHg== X-IronPort-AV: E=McAfee;i="6200,9189,9959"; a="195456506" X-IronPort-AV: E=Sophos;i="5.82,235,1613462400"; d="scan'208";a="195456506" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2021 19:05:27 -0700 IronPort-SDR: P+tRwGp2xVGtiG+MnEkaVDIKQ4ITyqvhioK5Hl+UFy8t15iPhJyNh6NPDkmjo2aWNAA2JQ/EUR /OtJhHZxgqpw== X-IronPort-AV: E=Sophos;i="5.82,235,1613462400"; d="scan'208";a="445356005" Received: from shwdenpg235.ccr.corp.intel.com ([10.240.182.60]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2021 19:05:25 -0700 From: Alvin Zhang To: haiyue.wang@intel.com, jia.guo@intel.com Cc: dev@dpdk.org, Alvin Zhang , stable@dpdk.org Date: Tue, 20 Apr 2021 10:05:20 +0800 Message-Id: <20210420020520.17936-1-alvinx.zhang@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 In-Reply-To: <20210416011407.29236-1-alvinx.zhang@intel.com> References: <20210416011407.29236-1-alvinx.zhang@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2] net/igc: fix Rx packet size error X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When DEV_RX_OFFLOAD_KEEP_CRC is enabled, the PMD will minus 4 bytes of CRC from the size of a packet, but the NIC will strip the CRC because the CRC strip bit in DVMOLR register is not cleared. This will cause the size of a packet to be 4 bytes less. This patch updates the CRC strip bit according to whether DEV_RX_OFFLOAD_KEEP_CRC is enabled. Fixes: a5aeb2b9e225 ("net/igc: support Rx and Tx") Cc: stable@dpdk.org Signed-off-by: Alvin Zhang Acked-by: Haiyue Wang Tested-by: Lingli Chen --- v2: Refine the codes. --- drivers/net/igc/igc_txrx.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/net/igc/igc_txrx.c b/drivers/net/igc/igc_txrx.c index 8eaed72..b5489ee 100644 --- a/drivers/net/igc/igc_txrx.c +++ b/drivers/net/igc/igc_txrx.c @@ -1291,20 +1291,24 @@ int eth_igc_rx_descriptor_status(void *rx_queue, uint16_t offset) * This needs to be done after enable. */ for (i = 0; i < dev->data->nb_rx_queues; i++) { + uint32_t dvmolr; + rxq = dev->data->rx_queues[i]; IGC_WRITE_REG(hw, IGC_RDH(rxq->reg_idx), 0); - IGC_WRITE_REG(hw, IGC_RDT(rxq->reg_idx), - rxq->nb_rx_desc - 1); + IGC_WRITE_REG(hw, IGC_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1); - /* strip queue vlan offload */ - if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { - uint32_t dvmolr; - dvmolr = IGC_READ_REG(hw, IGC_DVMOLR(rxq->queue_id)); + dvmolr = IGC_READ_REG(hw, IGC_DVMOLR(rxq->reg_idx)); + if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) + dvmolr |= IGC_DVMOLR_STRVLAN; + else + dvmolr &= ~IGC_DVMOLR_STRVLAN; - /* If vlan been stripped off, the CRC is meaningless. */ - dvmolr |= IGC_DVMOLR_STRVLAN | IGC_DVMOLR_STRCRC; - IGC_WRITE_REG(hw, IGC_DVMOLR(rxq->reg_idx), dvmolr); - } + if (offloads & DEV_RX_OFFLOAD_KEEP_CRC) + dvmolr &= ~IGC_DVMOLR_STRCRC; + else + dvmolr |= IGC_DVMOLR_STRCRC; + + IGC_WRITE_REG(hw, IGC_DVMOLR(rxq->reg_idx), dvmolr); } return 0; @@ -2267,12 +2271,10 @@ int eth_igc_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, reg_val = IGC_READ_REG(hw, IGC_DVMOLR(rx_queue_id)); if (on) { - /* If vlan been stripped off, the CRC is meaningless. */ - reg_val |= IGC_DVMOLR_STRVLAN | IGC_DVMOLR_STRCRC; + reg_val |= IGC_DVMOLR_STRVLAN; rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; } else { - reg_val &= ~(IGC_DVMOLR_STRVLAN | IGC_DVMOLR_HIDVLAN | - IGC_DVMOLR_STRCRC); + reg_val &= ~(IGC_DVMOLR_STRVLAN | IGC_DVMOLR_HIDVLAN); rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; }