From patchwork Fri Apr 16 01:14:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alvin Zhang X-Patchwork-Id: 91613 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7F646A0C3F; Fri, 16 Apr 2021 03:14:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 581AD1624C9; Fri, 16 Apr 2021 03:14:31 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 29A1C40140; Fri, 16 Apr 2021 03:14:28 +0200 (CEST) IronPort-SDR: YDHsK+j46auQ0SvRD4i2OkgLrMDRSnUy4wmAHopcNHEeJ4iH0UvBLbuCDaIFVZIf8AacFx4+5Q Unjpw4z9FZwA== X-IronPort-AV: E=McAfee;i="6200,9189,9955"; a="194999497" X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="194999497" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2021 18:14:26 -0700 IronPort-SDR: 8Cp0//ZDs2svyqet5+UPg3FhXl4BLFaNzv9dV9w6WitDeJtc8ennsUl2utWnyrT3TYha94tw2H LlR9wsRs6v3g== X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="453149764" Received: from shwdenpg235.ccr.corp.intel.com ([10.240.182.60]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2021 18:14:23 -0700 From: Alvin Zhang To: haiyue.wang@intel.com, jia.guo@intel.com Cc: dev@dpdk.org, Alvin Zhang , stable@dpdk.org Date: Fri, 16 Apr 2021 09:14:07 +0800 Message-Id: <20210416011407.29236-1-alvinx.zhang@intel.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH] net/igc: fix Rx packet size error X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When DEV_RX_OFFLOAD_KEEP_CRC is enabled, the PMD will minus 4 bytes of CRC from the size of a packet, but the NIC will strip the CRC because the CRC strip bit in DVMOLR register is not cleared. This will cause the size of a packet to be 4 bytes less. This patch updates the CRC strip bit according to whether DEV_RX_OFFLOAD_KEEP_CRC is enabled. Fixes: a5aeb2b9e225 ("net/igc: support Rx and Tx") Cc: stable@dpdk.org Signed-off-by: Alvin Zhang --- drivers/net/igc/igc_txrx.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/net/igc/igc_txrx.c b/drivers/net/igc/igc_txrx.c index c0a5d5e..68b102d 100644 --- a/drivers/net/igc/igc_txrx.c +++ b/drivers/net/igc/igc_txrx.c @@ -1290,20 +1290,24 @@ int eth_igc_rx_descriptor_status(void *rx_queue, uint16_t offset) * This needs to be done after enable. */ for (i = 0; i < dev->data->nb_rx_queues; i++) { + uint32_t dvmolr; + rxq = dev->data->rx_queues[i]; IGC_WRITE_REG(hw, IGC_RDH(rxq->reg_idx), 0); - IGC_WRITE_REG(hw, IGC_RDT(rxq->reg_idx), - rxq->nb_rx_desc - 1); + IGC_WRITE_REG(hw, IGC_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1); + + dvmolr = IGC_READ_REG(hw, IGC_DVMOLR(rxq->queue_id)); /* strip queue vlan offload */ - if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { - uint32_t dvmolr; - dvmolr = IGC_READ_REG(hw, IGC_DVMOLR(rxq->queue_id)); + dvmolr = (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) ? + (dvmolr | IGC_DVMOLR_STRVLAN) : + (dvmolr & ~IGC_DVMOLR_STRVLAN); - /* If vlan been stripped off, the CRC is meaningless. */ - dvmolr |= IGC_DVMOLR_STRVLAN | IGC_DVMOLR_STRCRC; - IGC_WRITE_REG(hw, IGC_DVMOLR(rxq->reg_idx), dvmolr); - } + dvmolr = (offloads & DEV_RX_OFFLOAD_KEEP_CRC) ? + (dvmolr & ~IGC_DVMOLR_STRCRC) : + (dvmolr | IGC_DVMOLR_STRCRC); + + IGC_WRITE_REG(hw, IGC_DVMOLR(rxq->reg_idx), dvmolr); } return 0;