From patchwork Thu Apr 8 09:50:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashwin Sekhar T K X-Patchwork-Id: 90864 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 656E4A0579; Thu, 8 Apr 2021 11:51:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 48658140FC2; Thu, 8 Apr 2021 11:51:14 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id BB53A141083 for ; Thu, 8 Apr 2021 11:51:13 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1389jbwk011022 for ; Thu, 8 Apr 2021 02:51:13 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=n6sxRHF0qyLReygfA6XpJiN5vRpsGIHobtURGk3feB4=; b=XNPxgTV0RDrs/F8yExomCoAFBKFu8/2d0sRMudysfX+u9MZKMhLwSQJcqpzN8ngjEqRZ /HumCHzq+dc/+R3yqKFjfxteXvGbgJ8sTlfWL9g+Zpa0eqlpZ5Zgg79H1nB7INAxkLvy Z9xyA2TtLRULK5aXiNClKJQYSGU8P2G6HSq1ILcDf8IH6iq2lHWROO4LHgWO46ijJ/I3 NT9HqnKuoXlg3XZZ/NbafiojtZPErp+267P2PH43Yd0lEEbKkj4hlEtoZGs2Y27hDpbG 9ruLIJbSkmTu6ut+p7B7UqzKiyVhM0oPN/hwhnmKnSGNmy3G7b1MKpdFFYyBCH1jugb8 dQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 37swewgf9n-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 08 Apr 2021 02:51:13 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 8 Apr 2021 02:51:10 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 8 Apr 2021 02:51:10 -0700 Received: from lab-ci-142.marvell.com (unknown [10.28.36.142]) by maili.marvell.com (Postfix) with ESMTP id BACB13F7044; Thu, 8 Apr 2021 02:51:07 -0700 (PDT) From: Ashwin Sekhar T K To: CC: , , , , , , Date: Thu, 8 Apr 2021 15:20:42 +0530 Message-ID: <20210408095049.3100322-5-asekhar@marvell.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210408095049.3100322-1-asekhar@marvell.com> References: <20210305162149.2196166-1-asekhar@marvell.com> <20210408095049.3100322-1-asekhar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: BIEFgWU8572sEtXJNwY4eRClMw_dSgEA X-Proofpoint-GUID: BIEFgWU8572sEtXJNwY4eRClMw_dSgEA X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-08_02:2021-04-08, 2021-04-08 signatures=0 Subject: [dpdk-dev] [PATCH v4 04/11] mempool/cnxk: register plt init callback X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Register the CNXk mempool plt init callback which will set the appropriate mempool ops to be used for the platform. Signed-off-by: Ashwin Sekhar T K --- drivers/mempool/cnxk/cnxk_mempool_ops.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/mempool/cnxk/cnxk_mempool_ops.c b/drivers/mempool/cnxk/cnxk_mempool_ops.c index 2ce1816c04..e8f64be76b 100644 --- a/drivers/mempool/cnxk/cnxk_mempool_ops.c +++ b/drivers/mempool/cnxk/cnxk_mempool_ops.c @@ -2,6 +2,7 @@ * Copyright(C) 2021 Marvell. */ +#include #include #include "roc_api.h" @@ -169,3 +170,17 @@ cnxk_mempool_populate(struct rte_mempool *mp, unsigned int max_objs, mp, RTE_MEMPOOL_POPULATE_F_ALIGN_OBJ, max_objs, vaddr, iova, len, obj_cb, obj_cb_arg); } + +static int +cnxk_mempool_plt_init(void) +{ + if (roc_model_is_cn10k() || roc_model_is_cn9k()) + rte_mbuf_set_platform_mempool_ops("cnxk_mempool_ops"); + + return 0; +} + +RTE_INIT(cnxk_mempool_ops_init) +{ + roc_plt_init_cb_register(cnxk_mempool_plt_init); +}