From patchwork Tue Apr 6 15:11:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashwin Sekhar T K X-Patchwork-Id: 90735 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4BB2CA0546; Tue, 6 Apr 2021 17:12:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E14D21411F7; Tue, 6 Apr 2021 17:11:46 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A30CB1411E9 for ; Tue, 6 Apr 2021 17:11:44 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 136F0RaI015105 for ; Tue, 6 Apr 2021 08:11:44 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=HpstXKB+6W62wiqjljt914QJoN0/ZmXdtWfYh1+iAfo=; b=NIq+ApJ7veqbv27MY/CC8yX8UG3um7HGU2lcV1JYQizQhzp6cqryRm4i7e0uCiyAfF6g 7414fQy3KBcl+kslqOmQyHC7nDDZ1jKcXScb/YU2HQIdF5J9oSYnX7P95qeIL60uyUxr BhKkPqnMZoC6OcMA9xs67TGYZFxxLkHHNgjUhnMlc7WfWBJMCtWOgAQ55KJ32KrXKAM8 NN3gb7qMLal+fA9J/uMqSKM33jmIm81lPRVgIQmXNxgGxmQ4xelO2JJWSJpmXuMeCRPV 3bkicd8BNll+1eO6rSV2Emxh+yAgv1c3s5E2kjHSDvKW7eh0wcj40aBaBOQAI6ji+Q5g 5g== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 37redma2qb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 06 Apr 2021 08:11:44 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 6 Apr 2021 08:11:42 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 6 Apr 2021 08:11:42 -0700 Received: from lab-ci-142.marvell.com (unknown [10.28.36.142]) by maili.marvell.com (Postfix) with ESMTP id C838B3F703F; Tue, 6 Apr 2021 08:11:39 -0700 (PDT) From: Ashwin Sekhar T K To: CC: , , , , , , Date: Tue, 6 Apr 2021 20:41:09 +0530 Message-ID: <20210406151115.1889455-6-asekhar@marvell.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210406151115.1889455-1-asekhar@marvell.com> References: <20210305162149.2196166-1-asekhar@marvell.com> <20210406151115.1889455-1-asekhar@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: Vd330TE6iMYj_CS6ArV1Fyg02TJBXVfX X-Proofpoint-ORIG-GUID: Vd330TE6iMYj_CS6ArV1Fyg02TJBXVfX X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-04-06_04:2021-04-01, 2021-04-06 signatures=0 Subject: [dpdk-dev] [PATCH v3 05/11] mempool/cnxk: add cn9k mempool ops X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add Marvell CN9k mempool ops and implement CN9k mempool alloc which makes sure that the element size always occupy odd number of cachelines to ensure even distribution among of elements among L1D cache sets. Signed-off-by: Pavan Nikhilesh Signed-off-by: Ashwin Sekhar T K --- drivers/mempool/cnxk/cn9k_mempool_ops.c | 54 +++++++++++++++++++++++++ drivers/mempool/cnxk/cnxk_mempool_ops.c | 4 +- drivers/mempool/cnxk/meson.build | 3 +- 3 files changed, 59 insertions(+), 2 deletions(-) create mode 100644 drivers/mempool/cnxk/cn9k_mempool_ops.c diff --git a/drivers/mempool/cnxk/cn9k_mempool_ops.c b/drivers/mempool/cnxk/cn9k_mempool_ops.c new file mode 100644 index 0000000000..f5ac163af9 --- /dev/null +++ b/drivers/mempool/cnxk/cn9k_mempool_ops.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include + +#include "roc_api.h" +#include "cnxk_mempool.h" + +static int +cn9k_mempool_alloc(struct rte_mempool *mp) +{ + size_t block_size, padding; + + block_size = mp->elt_size + mp->header_size + mp->trailer_size; + /* Align header size to ROC_ALIGN */ + if (mp->header_size % ROC_ALIGN != 0) { + padding = RTE_ALIGN_CEIL(mp->header_size, ROC_ALIGN) - + mp->header_size; + mp->header_size += padding; + block_size += padding; + } + + /* Align block size to ROC_ALIGN */ + if (block_size % ROC_ALIGN != 0) { + padding = RTE_ALIGN_CEIL(block_size, ROC_ALIGN) - block_size; + mp->trailer_size += padding; + block_size += padding; + } + + /* + * Marvell CN9k has 8 sets, 41 ways L1D cache, VA<9:7> bits dictate the + * set selection. Add additional padding to ensure that the element size + * always occupies odd number of cachelines to ensure even distribution + * of elements among L1D cache sets. + */ + padding = ((block_size / ROC_ALIGN) % 2) ? 0 : ROC_ALIGN; + mp->trailer_size += padding; + + return cnxk_mempool_alloc(mp); +} + +static struct rte_mempool_ops cn9k_mempool_ops = { + .name = "cn9k_mempool_ops", + .alloc = cn9k_mempool_alloc, + .free = cnxk_mempool_free, + .enqueue = cnxk_mempool_enq, + .dequeue = cnxk_mempool_deq, + .get_count = cnxk_mempool_get_count, + .calc_mem_size = cnxk_mempool_calc_mem_size, + .populate = cnxk_mempool_populate, +}; + +MEMPOOL_REGISTER_OPS(cn9k_mempool_ops); diff --git a/drivers/mempool/cnxk/cnxk_mempool_ops.c b/drivers/mempool/cnxk/cnxk_mempool_ops.c index e8f64be76b..d8ed37ec1a 100644 --- a/drivers/mempool/cnxk/cnxk_mempool_ops.c +++ b/drivers/mempool/cnxk/cnxk_mempool_ops.c @@ -174,7 +174,9 @@ cnxk_mempool_populate(struct rte_mempool *mp, unsigned int max_objs, static int cnxk_mempool_plt_init(void) { - if (roc_model_is_cn10k() || roc_model_is_cn9k()) + if (roc_model_is_cn9k()) + rte_mbuf_set_platform_mempool_ops("cn9k_mempool_ops"); + else if (roc_model_is_cn10k()) rte_mbuf_set_platform_mempool_ops("cnxk_mempool_ops"); return 0; diff --git a/drivers/mempool/cnxk/meson.build b/drivers/mempool/cnxk/meson.build index 52244e728b..ff31893ff4 100644 --- a/drivers/mempool/cnxk/meson.build +++ b/drivers/mempool/cnxk/meson.build @@ -9,6 +9,7 @@ if not is_linux or not dpdk_conf.get('RTE_ARCH_64') endif sources = files('cnxk_mempool.c', - 'cnxk_mempool_ops.c') + 'cnxk_mempool_ops.c', + 'cn9k_mempool_ops.c') deps += ['eal', 'mbuf', 'kvargs', 'bus_pci', 'common_cnxk', 'mempool']