From patchwork Tue Apr 6 14:41:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 90698 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 727C1A0546; Tue, 6 Apr 2021 16:45:47 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0C8C81410E7; Tue, 6 Apr 2021 16:43:05 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 55B671410CF for ; Tue, 6 Apr 2021 16:43:03 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 136Ee6M1000962 for ; Tue, 6 Apr 2021 07:43:02 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=h+xJOF8sGFnZoXimO3s4kbwecleDhsvpQ0fTH1Nj/uE=; b=ee+q/b+HzdtxH2CX3dSSqdPtpimV6nqUpBYnJddkQ9q5RqF8qoyVpJjD8xjucnKx8FsC i9Rgxtlp/zs1kPbfkrFCtlpVy9xuBx45cjt7pcLux3O1Auyoz3KRlFhaKR1RZuB0oENL SrFjsxENXg0WdY2QZtb8qTTLOK93wV6q0Gw/UfFEop9lLSREnWnDpxWX1I2fP49cOMqf GfA8M9g/OBwNIK3JPpT06SDwocgYfdxpy+4XeRcReFv2Axl91CZNh53ODozGDyAHtriR kzPzea+CqAfHR1FDfTIm85PcmTba74RtNHk3ddzpc6FVycIpbQ5dI6pES4nTynx+b9IZ yg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 37r72p30g1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 06 Apr 2021 07:43:02 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 6 Apr 2021 07:43:01 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 6 Apr 2021 07:43:01 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 3D89F3F7041; Tue, 6 Apr 2021 07:42:58 -0700 (PDT) From: Nithin Dabilpuram To: CC: , , , , , , , Vidya Sagar Velumuri Date: Tue, 6 Apr 2021 20:11:15 +0530 Message-ID: <20210406144144.19925-24-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210406144144.19925-1-ndabilpuram@marvell.com> References: <20210305133918.8005-1-ndabilpuram@marvell.com> <20210406144144.19925-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: hGJ7LYgsymeDbVktQ_7xnsNzHL02Buu- X-Proofpoint-ORIG-GUID: hGJ7LYgsymeDbVktQ_7xnsNzHL02Buu- X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-04-06_03:2021-04-01, 2021-04-06 signatures=0 Subject: [dpdk-dev] [PATCH v5 23/52] common/cnxk: add nix inline IPsec config API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Vidya Sagar Velumuri Add API to configure NIX block for inline IPSec. Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/roc_nix.c | 28 ++++++++++++++++++++++++++++ drivers/common/cnxk/roc_nix.h | 10 ++++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 39 insertions(+) diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index e64936e..0621976 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -81,6 +81,34 @@ roc_nix_get_pf_func(struct roc_nix *roc_nix) } int +roc_nix_lf_inl_ipsec_cfg(struct roc_nix *roc_nix, struct roc_nix_ipsec_cfg *cfg, + bool enb) +{ + struct nix *nix = roc_nix_to_nix_priv(roc_nix); + struct nix_inline_ipsec_lf_cfg *lf_cfg; + struct mbox *mbox = (&nix->dev)->mbox; + + lf_cfg = mbox_alloc_msg_nix_inline_ipsec_lf_cfg(mbox); + if (lf_cfg == NULL) + return -ENOSPC; + + if (enb) { + lf_cfg->enable = 1; + lf_cfg->sa_base_addr = cfg->iova; + lf_cfg->ipsec_cfg1.sa_idx_w = plt_log2_u32(cfg->max_sa); + lf_cfg->ipsec_cfg0.lenm1_max = roc_nix_max_pkt_len(roc_nix) - 1; + lf_cfg->ipsec_cfg1.sa_idx_max = cfg->max_sa - 1; + lf_cfg->ipsec_cfg0.sa_pow2_size = plt_log2_u32(cfg->sa_size); + lf_cfg->ipsec_cfg0.tag_const = cfg->tag_const; + lf_cfg->ipsec_cfg0.tt = cfg->tt; + } else { + lf_cfg->enable = 0; + } + + return mbox_process(mbox); +} + +int roc_nix_max_pkt_len(struct roc_nix *roc_nix) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 638f827..1c097cb 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -110,6 +110,14 @@ struct roc_nix_link_info { uint64_t port : 8; }; +struct roc_nix_ipsec_cfg { + uint32_t sa_size; + uint32_t tag_const; + plt_iova_t iova; + uint16_t max_sa; + uint8_t tt; +}; + /* Link status update callback */ typedef void (*link_status_t)(struct roc_nix *roc_nix, struct roc_nix_link_info *link); @@ -156,6 +164,8 @@ int __roc_api roc_nix_max_pkt_len(struct roc_nix *roc_nix); int __roc_api roc_nix_lf_alloc(struct roc_nix *roc_nix, uint32_t nb_rxq, uint32_t nb_txq, uint64_t rx_cfg); int __roc_api roc_nix_lf_free(struct roc_nix *roc_nix); +int __roc_api roc_nix_lf_inl_ipsec_cfg(struct roc_nix *roc_nix, + struct roc_nix_ipsec_cfg *cfg, bool enb); /* IRQ */ void __roc_api roc_nix_rx_queue_intr_enable(struct roc_nix *roc_nix, diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index bc6c988..a0df26a 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -28,6 +28,7 @@ INTERNAL { roc_nix_is_sdp; roc_nix_is_vf_or_sdp; roc_nix_lf_alloc; + roc_nix_lf_inl_ipsec_cfg; roc_nix_lf_free; roc_nix_mac_addr_add; roc_nix_mac_addr_del;