From patchwork Fri Apr 2 02:07:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Kozyrev X-Patchwork-Id: 90442 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 95DC8A0548; Fri, 2 Apr 2021 04:07:49 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7A3BE40F35; Fri, 2 Apr 2021 04:07:49 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 21BD240150 for ; Fri, 2 Apr 2021 04:07:48 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from akozyrev@nvidia.com) with SMTP; 2 Apr 2021 05:07:42 +0300 Received: from nvidia.com (pegasus02.mtr.labs.mlnx [10.210.16.122]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 13227gaK016600; Fri, 2 Apr 2021 05:07:42 +0300 From: Alexander Kozyrev To: dev@dpdk.org Cc: stable@dpdk.org, rasland@nvidia.com, viacheslavo@nvidia.com Date: Fri, 2 Apr 2021 02:07:41 +0000 Message-Id: <20210402020741.25715-1-akozyrev@nvidia.com> X-Mailer: git-send-email 2.24.1 MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH] net/mlx5: fix modify field action endianness X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Converting modify_field action masks to the big endian format is wrong for small (less than 4 bytes) fields. Use the BE conversions appropriate for a field size, not rte_cpu_to_be_32 for everything. Fixes: 7ffda9dbed ("net/mlx5: adjust modify field action endianness") Cc: stable@dpdk.org Signed-off-by: Alexander Kozyrev Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow_dv.c | 39 +++++++++++---------------------- 1 file changed, 13 insertions(+), 26 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 533dadf07b..bf1ab1b712 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1360,8 +1360,7 @@ mlx5_flow_field_id_to_modify_info } info[idx] = (struct field_modify_info){2, 4 * idx, MLX5_MODI_OUT_DMAC_15_0}; - mask[idx] = rte_cpu_to_be_32(0x0000ffff >> - (16 - width)); + mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width)); } else { if (data->offset < 32) info[idx++] = (struct field_modify_info){4, 0, @@ -1390,8 +1389,7 @@ mlx5_flow_field_id_to_modify_info } info[idx] = (struct field_modify_info){2, 4 * idx, MLX5_MODI_OUT_SMAC_15_0}; - mask[idx] = rte_cpu_to_be_32(0x0000ffff >> - (16 - width)); + mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width)); } else { if (data->offset < 32) info[idx++] = (struct field_modify_info){4, 0, @@ -1407,29 +1405,25 @@ mlx5_flow_field_id_to_modify_info info[idx] = (struct field_modify_info){2, 0, MLX5_MODI_OUT_FIRST_VID}; if (mask) - mask[idx] = rte_cpu_to_be_32(0x00000fff >> - (12 - width)); + mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width)); break; case RTE_FLOW_FIELD_MAC_TYPE: info[idx] = (struct field_modify_info){2, 0, MLX5_MODI_OUT_ETHERTYPE}; if (mask) - mask[idx] = rte_cpu_to_be_32(0x0000ffff >> - (16 - width)); + mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width)); break; case RTE_FLOW_FIELD_IPV4_DSCP: info[idx] = (struct field_modify_info){1, 0, MLX5_MODI_OUT_IP_DSCP}; if (mask) - mask[idx] = rte_cpu_to_be_32(0x0000003f >> - (6 - width)); + mask[idx] = 0x3f >> (6 - width); break; case RTE_FLOW_FIELD_IPV4_TTL: info[idx] = (struct field_modify_info){1, 0, MLX5_MODI_OUT_IPV4_TTL}; if (mask) - mask[idx] = rte_cpu_to_be_32(0x000000ff >> - (8 - width)); + mask[idx] = 0xff >> (8 - width); break; case RTE_FLOW_FIELD_IPV4_SRC: info[idx] = (struct field_modify_info){4, 0, @@ -1449,15 +1443,13 @@ mlx5_flow_field_id_to_modify_info info[idx] = (struct field_modify_info){1, 0, MLX5_MODI_OUT_IP_DSCP}; if (mask) - mask[idx] = rte_cpu_to_be_32(0x0000003f >> - (6 - width)); + mask[idx] = 0x3f >> (6 - width); break; case RTE_FLOW_FIELD_IPV6_HOPLIMIT: info[idx] = (struct field_modify_info){1, 0, MLX5_MODI_OUT_IPV6_HOPLIMIT}; if (mask) - mask[idx] = rte_cpu_to_be_32(0x000000ff >> - (8 - width)); + mask[idx] = 0xff >> (8 - width); break; case RTE_FLOW_FIELD_IPV6_SRC: if (mask) { @@ -1605,15 +1597,13 @@ mlx5_flow_field_id_to_modify_info info[idx] = (struct field_modify_info){2, 0, MLX5_MODI_OUT_TCP_SPORT}; if (mask) - mask[idx] = rte_cpu_to_be_32(0x0000ffff >> - (16 - width)); + mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width)); break; case RTE_FLOW_FIELD_TCP_PORT_DST: info[idx] = (struct field_modify_info){2, 0, MLX5_MODI_OUT_TCP_DPORT}; if (mask) - mask[idx] = rte_cpu_to_be_32(0x0000ffff >> - (16 - width)); + mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width)); break; case RTE_FLOW_FIELD_TCP_SEQ_NUM: info[idx] = (struct field_modify_info){4, 0, @@ -1633,22 +1623,19 @@ mlx5_flow_field_id_to_modify_info info[idx] = (struct field_modify_info){1, 0, MLX5_MODI_OUT_TCP_FLAGS}; if (mask) - mask[idx] = rte_cpu_to_be_32(0x0000003f >> - (6 - width)); + mask[idx] = 0x3f >> (6 - width); break; case RTE_FLOW_FIELD_UDP_PORT_SRC: info[idx] = (struct field_modify_info){2, 0, MLX5_MODI_OUT_UDP_SPORT}; if (mask) - mask[idx] = rte_cpu_to_be_32(0x0000ffff >> - (16 - width)); + mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width)); break; case RTE_FLOW_FIELD_UDP_PORT_DST: info[idx] = (struct field_modify_info){2, 0, MLX5_MODI_OUT_UDP_DPORT}; if (mask) - mask[idx] = rte_cpu_to_be_32(0x0000ffff >> - (16 - width)); + mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width)); break; case RTE_FLOW_FIELD_VXLAN_VNI: /* not supported yet */