diff mbox series

net/mlx5: fix modify field action endianness

Message ID 20210402020741.25715-1-akozyrev@nvidia.com (mailing list archive)
State Accepted
Delegated to: Raslan Darawsheh
Headers show
Series net/mlx5: fix modify field action endianness | expand

Checks

Context Check Description
ci/iol-testing success Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-abi-testing success Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/travis-robot success travis build: passed
ci/intel-Testing success Testing PASS
ci/Intel-compilation success Compilation OK
ci/checkpatch success coding style OK

Commit Message

Alexander Kozyrev April 2, 2021, 2:07 a.m. UTC
Converting modify_field action masks to the big endian format is wrong
for small (less than 4 bytes) fields. Use the BE conversions appropriate
for a field size, not rte_cpu_to_be_32 for everything.

Fixes: 7ffda9dbed ("net/mlx5: adjust modify field action endianness")
Cc: stable@dpdk.org

Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_dv.c | 39 +++++++++++----------------------
 1 file changed, 13 insertions(+), 26 deletions(-)

Comments

Slava Ovsiienko April 7, 2021, 3:06 p.m. UTC | #1
> -----Original Message-----
> From: Alexander Kozyrev <akozyrev@nvidia.com>
> Sent: Friday, April 2, 2021 5:08
> To: dev@dpdk.org
> Cc: stable@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>
> Subject: [PATCH] net/mlx5: fix modify field action endianness
> 
> Converting modify_field action masks to the big endian format is wrong for
> small (less than 4 bytes) fields. Use the BE conversions appropriate for a field
> size, not rte_cpu_to_be_32 for everything.
> 
> Fixes: 7ffda9dbed ("net/mlx5: adjust modify field action endianness")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Raslan Darawsheh April 11, 2021, 7:22 a.m. UTC | #2
Hi,

> -----Original Message-----
> From: Alexander Kozyrev <akozyrev@nvidia.com>
> Sent: Friday, April 2, 2021 5:08 AM
> To: dev@dpdk.org
> Cc: stable@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>
> Subject: [PATCH] net/mlx5: fix modify field action endianness
> 
> Converting modify_field action masks to the big endian format is wrong
> for small (less than 4 bytes) fields. Use the BE conversions appropriate
> for a field size, not rte_cpu_to_be_32 for everything.
> 
> Fixes: 7ffda9dbed ("net/mlx5: adjust modify field action endianness")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
> ---

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 533dadf07b..bf1ab1b712 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -1360,8 +1360,7 @@  mlx5_flow_field_id_to_modify_info
 			}
 			info[idx] = (struct field_modify_info){2, 4 * idx,
 						MLX5_MODI_OUT_DMAC_15_0};
-			mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
-						     (16 - width));
+			mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
 		} else {
 			if (data->offset < 32)
 				info[idx++] = (struct field_modify_info){4, 0,
@@ -1390,8 +1389,7 @@  mlx5_flow_field_id_to_modify_info
 			}
 			info[idx] = (struct field_modify_info){2, 4 * idx,
 						MLX5_MODI_OUT_SMAC_15_0};
-			mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
-						     (16 - width));
+			mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
 		} else {
 			if (data->offset < 32)
 				info[idx++] = (struct field_modify_info){4, 0,
@@ -1407,29 +1405,25 @@  mlx5_flow_field_id_to_modify_info
 		info[idx] = (struct field_modify_info){2, 0,
 					MLX5_MODI_OUT_FIRST_VID};
 		if (mask)
-			mask[idx] = rte_cpu_to_be_32(0x00000fff >>
-						     (12 - width));
+			mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
 		break;
 	case RTE_FLOW_FIELD_MAC_TYPE:
 		info[idx] = (struct field_modify_info){2, 0,
 					MLX5_MODI_OUT_ETHERTYPE};
 		if (mask)
-			mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
-						     (16 - width));
+			mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
 		break;
 	case RTE_FLOW_FIELD_IPV4_DSCP:
 		info[idx] = (struct field_modify_info){1, 0,
 					MLX5_MODI_OUT_IP_DSCP};
 		if (mask)
-			mask[idx] = rte_cpu_to_be_32(0x0000003f >>
-						     (6 - width));
+			mask[idx] = 0x3f >> (6 - width);
 		break;
 	case RTE_FLOW_FIELD_IPV4_TTL:
 		info[idx] = (struct field_modify_info){1, 0,
 					MLX5_MODI_OUT_IPV4_TTL};
 		if (mask)
-			mask[idx] = rte_cpu_to_be_32(0x000000ff >>
-						     (8 - width));
+			mask[idx] = 0xff >> (8 - width);
 		break;
 	case RTE_FLOW_FIELD_IPV4_SRC:
 		info[idx] = (struct field_modify_info){4, 0,
@@ -1449,15 +1443,13 @@  mlx5_flow_field_id_to_modify_info
 		info[idx] = (struct field_modify_info){1, 0,
 					MLX5_MODI_OUT_IP_DSCP};
 		if (mask)
-			mask[idx] = rte_cpu_to_be_32(0x0000003f >>
-						     (6 - width));
+			mask[idx] = 0x3f >> (6 - width);
 		break;
 	case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
 		info[idx] = (struct field_modify_info){1, 0,
 					MLX5_MODI_OUT_IPV6_HOPLIMIT};
 		if (mask)
-			mask[idx] = rte_cpu_to_be_32(0x000000ff >>
-						     (8 - width));
+			mask[idx] = 0xff >> (8 - width);
 		break;
 	case RTE_FLOW_FIELD_IPV6_SRC:
 		if (mask) {
@@ -1605,15 +1597,13 @@  mlx5_flow_field_id_to_modify_info
 		info[idx] = (struct field_modify_info){2, 0,
 					MLX5_MODI_OUT_TCP_SPORT};
 		if (mask)
-			mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
-						     (16 - width));
+			mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
 		break;
 	case RTE_FLOW_FIELD_TCP_PORT_DST:
 		info[idx] = (struct field_modify_info){2, 0,
 					MLX5_MODI_OUT_TCP_DPORT};
 		if (mask)
-			mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
-						     (16 - width));
+			mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
 		break;
 	case RTE_FLOW_FIELD_TCP_SEQ_NUM:
 		info[idx] = (struct field_modify_info){4, 0,
@@ -1633,22 +1623,19 @@  mlx5_flow_field_id_to_modify_info
 		info[idx] = (struct field_modify_info){1, 0,
 					MLX5_MODI_OUT_TCP_FLAGS};
 		if (mask)
-			mask[idx] = rte_cpu_to_be_32(0x0000003f >>
-						     (6 - width));
+			mask[idx] = 0x3f >> (6 - width);
 		break;
 	case RTE_FLOW_FIELD_UDP_PORT_SRC:
 		info[idx] = (struct field_modify_info){2, 0,
 					MLX5_MODI_OUT_UDP_SPORT};
 		if (mask)
-			mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
-						     (16 - width));
+			mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
 		break;
 	case RTE_FLOW_FIELD_UDP_PORT_DST:
 		info[idx] = (struct field_modify_info){2, 0,
 					MLX5_MODI_OUT_UDP_DPORT};
 		if (mask)
-			mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
-						     (16 - width));
+			mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
 		break;
 	case RTE_FLOW_FIELD_VXLAN_VNI:
 		/* not supported yet */