From patchwork Thu Apr 1 12:38:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 90422 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 417A9A0548; Thu, 1 Apr 2021 14:45:50 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D47531412F6; Thu, 1 Apr 2021 14:41:06 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 7DDE51411E8 for ; Thu, 1 Apr 2021 14:41:05 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 131CPLXw019083 for ; Thu, 1 Apr 2021 05:41:05 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=/ZefIrSiGDfS6jmP3F+6kzn+LjTwFprzonmmPB10vbQ=; b=f4gHkwwO42IL3RCKxfrd6QSoNkf1IE6GwJxHEJ+wEXNFayVIs5yLnAFPTlHuQt2ChD5D PGyF4YcZ18tQxlhTFuMaw4i8cE1EBU8kI0Z3LZTnsu/CF6snLDWzrV2/b8SjlYRmDrXL fTZBp7tVLPdLHS9uW2ybw8fdPzlYPcbDRl8lSr6Bes/0llFyfjFpL07WNxhPzAQKlB3y p7aoRG5IbefOIK/4qyIZDn0wmxWOE77S2M/KLiy478PGge8WXUEbocIMAJQsA5vWM1e+ Sb9n4+Dl0e96e1sqsEa5adwBo5X3AKtajEXQuurtEGAFn2ZXnRvAPBjd4B6sUz2YQZoq HQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 37n28jje80-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 01 Apr 2021 05:41:04 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 1 Apr 2021 05:41:02 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 1 Apr 2021 05:41:02 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id E421E3F7048; Thu, 1 Apr 2021 05:40:59 -0700 (PDT) From: Nithin Dabilpuram To: CC: , , , , , , Date: Thu, 1 Apr 2021 18:08:14 +0530 Message-ID: <20210401123817.14348-50-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210401123817.14348-1-ndabilpuram@marvell.com> References: <20210305133918.8005-1-ndabilpuram@marvell.com> <20210401123817.14348-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 3Pbg9yXPKSoWjwc3OJ_CRnxj6NmN3iZR X-Proofpoint-ORIG-GUID: 3Pbg9yXPKSoWjwc3OJ_CRnxj6NmN3iZR X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-04-01_05:2021-03-31, 2021-04-01 signatures=0 Subject: [dpdk-dev] [PATCH v3 49/52] common/cnxk: add sso debug support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add sso debug dump support. This dumps all SSO LF register values to a given file handle. Signed-off-by: Pavan Nikhilesh --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_sso.h | 4 +++ drivers/common/cnxk/roc_sso_debug.c | 68 +++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 1 + 4 files changed, 74 insertions(+) create mode 100644 drivers/common/cnxk/roc_sso_debug.c diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index d28e273..e6e2ad3 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -40,6 +40,7 @@ sources = files('roc_dev.c', 'roc_npc_utils.c', 'roc_platform.c', 'roc_sso.c', + 'roc_sso_debug.c', 'roc_sso_irq.c', 'roc_utils.c') includes += include_directories('../../bus/pci') diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index ed2713c..f85799b 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -58,4 +58,8 @@ uintptr_t __roc_api roc_sso_hws_base_get(struct roc_sso *roc_sso, uint8_t hws); uintptr_t __roc_api roc_sso_hwgrp_base_get(struct roc_sso *roc_sso, uint16_t hwgrp); +/* Debug */ +void __roc_api roc_sso_dump(struct roc_sso *roc_sso, uint8_t nb_hws, + uint16_t hwgrp, FILE *f); + #endif /* _ROC_SSOW_H_ */ diff --git a/drivers/common/cnxk/roc_sso_debug.c b/drivers/common/cnxk/roc_sso_debug.c new file mode 100644 index 0000000..7571bad --- /dev/null +++ b/drivers/common/cnxk/roc_sso_debug.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "roc_api.h" +#include "roc_priv.h" + +static void +sso_hws_dump(uintptr_t base, FILE *f) +{ + fprintf(f, "SSOW_LF_GWS Base addr 0x%" PRIx64 "\n", (uint64_t)base); + fprintf(f, "SSOW_LF_GWS_LINKS 0x%" PRIx64 "\n", + plt_read64(base + SSOW_LF_GWS_LINKS)); + fprintf(f, "SSOW_LF_GWS_PENDWQP 0x%" PRIx64 "\n", + plt_read64(base + SSOW_LF_GWS_PENDWQP)); + fprintf(f, "SSOW_LF_GWS_PENDSTATE 0x%" PRIx64 "\n", + plt_read64(base + SSOW_LF_GWS_PENDSTATE)); + fprintf(f, "SSOW_LF_GWS_NW_TIM 0x%" PRIx64 "\n", + plt_read64(base + SSOW_LF_GWS_NW_TIM)); + fprintf(f, "SSOW_LF_GWS_TAG 0x%" PRIx64 "\n", + plt_read64(base + SSOW_LF_GWS_TAG)); + fprintf(f, "SSOW_LF_GWS_WQP 0x%" PRIx64 "\n", + plt_read64(base + SSOW_LF_GWS_TAG)); + fprintf(f, "SSOW_LF_GWS_SWTP 0x%" PRIx64 "\n", + plt_read64(base + SSOW_LF_GWS_SWTP)); + fprintf(f, "SSOW_LF_GWS_PENDTAG 0x%" PRIx64 "\n", + plt_read64(base + SSOW_LF_GWS_PENDTAG)); +} + +static void +sso_hwgrp_dump(uintptr_t base, FILE *f) +{ + fprintf(f, "SSO_LF_GGRP Base addr 0x%" PRIx64 "\n", (uint64_t)base); + fprintf(f, "SSO_LF_GGRP_QCTL 0x%" PRIx64 "\n", + plt_read64(base + SSO_LF_GGRP_QCTL)); + fprintf(f, "SSO_LF_GGRP_XAQ_CNT 0x%" PRIx64 "\n", + plt_read64(base + SSO_LF_GGRP_XAQ_CNT)); + fprintf(f, "SSO_LF_GGRP_INT_THR 0x%" PRIx64 "\n", + plt_read64(base + SSO_LF_GGRP_INT_THR)); + fprintf(f, "SSO_LF_GGRP_INT_CNT 0x%" PRIX64 "\n", + plt_read64(base + SSO_LF_GGRP_INT_CNT)); + fprintf(f, "SSO_LF_GGRP_AQ_CNT 0x%" PRIX64 "\n", + plt_read64(base + SSO_LF_GGRP_AQ_CNT)); + fprintf(f, "SSO_LF_GGRP_AQ_THR 0x%" PRIX64 "\n", + plt_read64(base + SSO_LF_GGRP_AQ_THR)); + fprintf(f, "SSO_LF_GGRP_MISC_CNT 0x%" PRIx64 "\n", + plt_read64(base + SSO_LF_GGRP_MISC_CNT)); +} + +void +roc_sso_dump(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t hwgrp, FILE *f) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + uintptr_t base; + int i; + + /* Dump SSOW registers */ + for (i = 0; i < nb_hws; i++) { + base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12); + sso_hws_dump(base, f); + } + + /* Dump SSO registers */ + for (i = 0; i < hwgrp; i++) { + base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | i << 12); + sso_hwgrp_dump(base, f); + } +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 3e3d9dc..e93d623 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -176,6 +176,7 @@ INTERNAL { roc_plt_init; roc_sso_dev_fini; roc_sso_dev_init; + roc_sso_dump; roc_sso_hwgrp_alloc_xaq; roc_sso_hwgrp_base_get; roc_sso_hwgrp_hws_link_status;