From patchwork Thu Apr 1 12:38:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 90420 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D01A0A0548; Thu, 1 Apr 2021 14:45:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C54BF1412E7; Thu, 1 Apr 2021 14:41:00 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 072BC1412E7 for ; Thu, 1 Apr 2021 14:40:58 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 131CPLGn019096 for ; Thu, 1 Apr 2021 05:40:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=MJb5awcBQjXlf9k6fs02GmMFlJ4BSHx+cWDcI2FDFcs=; b=SkO/Ao3FJ1opM4QACnNhZyZ62Ck+q9X2s3lY/KX1i+qbC5T9xXDrDpdf8qafxQj02QRH KY9tFPris9CP2O82U0/9yqGJEdQF8ElhI9T/AjsK+wvLi3y0ZxL+uIKDVOXPrl7mX0gu oEGl0HKqQ7PjafDe+MfyReNDOI8eXIUwLP+6pP9Za5YkBNypwMc917KP24yURpB2sX7R xEtVhKN5sLYeiNNdAvrwYRgQd5f3ip5L3AXNMBR4Z3FtedRY9PknmHKaIy9f9rfNYeSX RcmZhdzJvFw9ZMIApYT9cB8WazSmqAweGEjCW1KUbZL0IZ/8f0+E1K+RCpWdXukwGgSp 3A== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 37n28jje7k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 01 Apr 2021 05:40:58 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 1 Apr 2021 05:40:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 1 Apr 2021 05:40:56 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id F305E3F7044; Thu, 1 Apr 2021 05:40:53 -0700 (PDT) From: Nithin Dabilpuram To: CC: , , , , , , Date: Thu, 1 Apr 2021 18:08:12 +0530 Message-ID: <20210401123817.14348-48-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210401123817.14348-1-ndabilpuram@marvell.com> References: <20210305133918.8005-1-ndabilpuram@marvell.com> <20210401123817.14348-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ocwRa_uexkOs7iwazMYdpmwEtT7W8J_M X-Proofpoint-ORIG-GUID: ocwRa_uexkOs7iwazMYdpmwEtT7W8J_M X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-04-01_05:2021-03-31, 2021-04-01 signatures=0 Subject: [dpdk-dev] [PATCH v3 47/52] common/cnxk: add sso hwgrp interface X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add SSO HWGRP interface for configuring XAQ pool, setting priority and internal HW buffer limits for each HWGRP. Signed-off-by: Pavan Nikhilesh --- drivers/common/cnxk/roc_sso.c | 110 ++++++++++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_sso.h | 21 ++++++++ drivers/common/cnxk/version.map | 6 +++ 3 files changed, 137 insertions(+) diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index ba9dc3b..f4c4e5b 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -194,6 +194,14 @@ roc_sso_hws_base_get(struct roc_sso *roc_sso, uint8_t hws) return dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | hws << 12); } +uintptr_t +roc_sso_hwgrp_base_get(struct roc_sso *roc_sso, uint16_t hwgrp) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + + return dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | hwgrp << 12); +} + uint64_t roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns) { @@ -251,6 +259,108 @@ roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], } int +roc_sso_hwgrp_hws_link_status(struct roc_sso *roc_sso, uint8_t hws, + uint16_t hwgrp) +{ + struct sso *sso; + + sso = roc_sso_to_sso_priv(roc_sso); + return plt_bitmap_get(sso->link_map[hws], hwgrp); +} + +int +roc_sso_hwgrp_qos_config(struct roc_sso *roc_sso, struct roc_sso_hwgrp_qos *qos, + uint8_t nb_qos, uint32_t nb_xaq) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + struct sso_grp_qos_cfg *req; + int i, rc; + + for (i = 0; i < nb_qos; i++) { + uint8_t xaq_prcnt = qos[i].xaq_prcnt; + uint8_t iaq_prcnt = qos[i].iaq_prcnt; + uint8_t taq_prcnt = qos[i].taq_prcnt; + + req = mbox_alloc_msg_sso_grp_qos_config(dev->mbox); + if (req == NULL) { + rc = mbox_process(dev->mbox); + if (rc < 0) + return rc; + req = mbox_alloc_msg_sso_grp_qos_config(dev->mbox); + if (req == NULL) + return -ENOSPC; + } + req->grp = qos[i].hwgrp; + req->xaq_limit = (nb_xaq * (xaq_prcnt ? xaq_prcnt : 100)) / 100; + req->taq_thr = (SSO_HWGRP_IAQ_MAX_THR_MASK * + (iaq_prcnt ? iaq_prcnt : 100)) / + 100; + req->iaq_thr = (SSO_HWGRP_TAQ_MAX_THR_MASK * + (taq_prcnt ? taq_prcnt : 100)) / + 100; + } + + return mbox_process(dev->mbox); +} + +int +roc_sso_hwgrp_alloc_xaq(struct roc_sso *roc_sso, uint32_t npa_aura_id, + uint16_t hwgrps) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + struct sso_hw_setconfig *req; + int rc = -ENOSPC; + + req = mbox_alloc_msg_sso_hw_setconfig(dev->mbox); + if (req == NULL) + return rc; + req->npa_pf_func = idev_npa_pffunc_get(); + req->npa_aura_id = npa_aura_id; + req->hwgrps = hwgrps; + + return mbox_process(dev->mbox); +} + +int +roc_sso_hwgrp_release_xaq(struct roc_sso *roc_sso, uint16_t hwgrps) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + struct sso_hw_xaq_release *req; + + req = mbox_alloc_msg_sso_hw_release_xaq_aura(dev->mbox); + if (req == NULL) + return -EINVAL; + req->hwgrps = hwgrps; + + return mbox_process(dev->mbox); +} + +int +roc_sso_hwgrp_set_priority(struct roc_sso *roc_sso, uint16_t hwgrp, + uint8_t weight, uint8_t affinity, uint8_t priority) +{ + struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev; + struct sso_grp_priority *req; + int rc = -ENOSPC; + + req = mbox_alloc_msg_sso_grp_set_priority(dev->mbox); + if (req == NULL) + return rc; + req->grp = hwgrp; + req->weight = weight; + req->affinity = affinity; + req->priority = priority; + + rc = mbox_process(dev->mbox); + if (rc < 0) + return rc; + plt_sso_dbg("HWGRP %d weight %d affinity %d priority %d", hwgrp, weight, + affinity, priority); + + return 0; +} + +int roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp) { struct sso_lf_alloc_rsp *rsp_hwgrp; diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h index 7236045..ed2713c 100644 --- a/drivers/common/cnxk/roc_sso.h +++ b/drivers/common/cnxk/roc_sso.h @@ -5,6 +5,13 @@ #ifndef _ROC_SSO_H_ #define _ROC_SSO_H_ +struct roc_sso_hwgrp_qos { + uint16_t hwgrp; + uint8_t xaq_prcnt; + uint8_t iaq_prcnt; + uint8_t taq_prcnt; +}; + struct roc_sso { struct plt_pci_device *pci_dev; /* Public data. */ @@ -30,11 +37,25 @@ int __roc_api roc_sso_dev_fini(struct roc_sso *roc_sso); int __roc_api roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp); void __roc_api roc_sso_rsrc_fini(struct roc_sso *roc_sso); +int __roc_api roc_sso_hwgrp_qos_config(struct roc_sso *roc_sso, + struct roc_sso_hwgrp_qos *qos, + uint8_t nb_qos, uint32_t nb_xaq); +int __roc_api roc_sso_hwgrp_alloc_xaq(struct roc_sso *roc_sso, + uint32_t npa_aura_id, uint16_t hwgrps); +int __roc_api roc_sso_hwgrp_release_xaq(struct roc_sso *roc_sso, + uint16_t hwgrps); +int __roc_api roc_sso_hwgrp_set_priority(struct roc_sso *roc_sso, + uint16_t hwgrp, uint8_t weight, + uint8_t affinity, uint8_t priority); uint64_t __roc_api roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns); int __roc_api roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], uint16_t nb_hwgrp); int __roc_api roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[], uint16_t nb_hwgrp); +int __roc_api roc_sso_hwgrp_hws_link_status(struct roc_sso *roc_sso, + uint8_t hws, uint16_t hwgrp); uintptr_t __roc_api roc_sso_hws_base_get(struct roc_sso *roc_sso, uint8_t hws); +uintptr_t __roc_api roc_sso_hwgrp_base_get(struct roc_sso *roc_sso, + uint16_t hwgrp); #endif /* _ROC_SSOW_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 2656e11..3e3d9dc 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -176,6 +176,12 @@ INTERNAL { roc_plt_init; roc_sso_dev_fini; roc_sso_dev_init; + roc_sso_hwgrp_alloc_xaq; + roc_sso_hwgrp_base_get; + roc_sso_hwgrp_hws_link_status; + roc_sso_hwgrp_qos_config; + roc_sso_hwgrp_release_xaq; + roc_sso_hwgrp_set_priority; roc_sso_hws_base_get; roc_sso_hws_link; roc_sso_hws_unlink;