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[v1,2/4] net/mlx4: replace SMP barrier with C11 barriers

Message ID 20210318071840.359957-3-feifei.wang2@arm.com (mailing list archive)
State Superseded
Delegated to: Raslan Darawsheh
Headers show
Series refactor SMP barriers for net/mlx | expand


Context Check Description
ci/checkpatch success coding style OK

Commit Message

Feifei Wang March 18, 2021, 7:18 a.m. UTC
Replace SMP barrier with atomic thread fence.

Signed-off-by: Feifei Wang <feifei.wang2@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
 drivers/net/mlx4/mlx4_mr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/drivers/net/mlx4/mlx4_mr.c b/drivers/net/mlx4/mlx4_mr.c
index cfd7d4a9c..503e8a7bb 100644
--- a/drivers/net/mlx4/mlx4_mr.c
+++ b/drivers/net/mlx4/mlx4_mr.c
@@ -951,11 +951,11 @@  mlx4_mr_mem_event_free_cb(struct rte_eth_dev *dev, const void *addr, size_t len)
 		/* Flush local caches by propagating invalidation across cores.
-		 * rte_smp_wmb is to keep the order that dev_gen updated before
+		 * release-fence is to keep the order that dev_gen updated before
 		 * rebuilding global cache. Therefore, other core can flush their
 		 * local cache on time.
-		rte_smp_wmb();
+		rte_atomic_thread_fence(__ATOMIC_RELEASE);