From patchwork Sun Mar 14 11:58:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Slava Ovsiienko X-Patchwork-Id: 89078 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E5237A0524; Sun, 14 Mar 2021 12:58:40 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id ABA8D1608F0; Sun, 14 Mar 2021 12:58:16 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id 0CF7E160840 for ; Sun, 14 Mar 2021 12:58:09 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from viacheslavo@nvidia.com) with SMTP; 14 Mar 2021 13:58:08 +0200 Received: from nvidia.com (pegasus12.mtr.labs.mlnx [10.210.17.40]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 12EBw4YD004594; Sun, 14 Mar 2021 13:58:08 +0200 From: Viacheslav Ovsiienko To: dev@dpdk.org Cc: rasland@nvidia.com, matan@nvidia.com, orika@nvidia.com, stable@dpdk.org Date: Sun, 14 Mar 2021 11:58:03 +0000 Message-Id: <20210314115803.3110-6-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210314115803.3110-1-viacheslavo@nvidia.com> References: <20210307100251.22538-1-viacheslavo@nvidia.com> <20210314115803.3110-1-viacheslavo@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 5/5] compress/mlx5: add timestamp format support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds support for the timestamp format settings for the receive and send queues. If the firmware version x.30.1000 or above is installed and the NIC timestamps are configured with the real-time format, the default zero values for newly added fields cause the queue creation to fail. The patch queries the timestamp formats supported by the hardware and sets the configuration values in queue context accordingly. Fixes: 8619fcd5161b ("compress/mlx5: support queue pair operations") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko Acked-by: Matan Azrad Acked-by: Ori Kam --- drivers/compress/mlx5/mlx5_compress.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 46255ab5e0..fdd4e44848 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -43,6 +43,7 @@ struct mlx5_compress_priv { void *uar; uint32_t pdn; /* Protection Domain number. */ uint8_t min_block_size; + uint8_t sq_ts_format; /* Whether SQ supports timestamp formats. */ /* Minimum huffman block size supported by the device. */ struct ibv_pd *pd; struct rte_compressdev_config dev_config; @@ -245,6 +246,7 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, goto err; } sq_attr.cqn = qp->cq.cq->id; + sq_attr.ts_format = mlx5_ts_format_conv(priv->sq_ts_format); ret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr, socket_id); if (ret != 0) { @@ -814,6 +816,7 @@ mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv, priv->pci_dev = pci_dev; priv->cdev = cdev; priv->min_block_size = att.compress_min_block_size; + priv->sq_ts_format = att.sq_ts_format; if (mlx5_compress_hw_global_prepare(priv) != 0) { rte_compressdev_pmd_destroy(priv->cdev); claim_zero(mlx5_glue->close_device(priv->ctx));