From patchwork Fri Mar 12 05:58:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Khaparde X-Patchwork-Id: 88990 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 262A6A0547; Fri, 12 Mar 2021 06:59:44 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7F1B11608A1; Fri, 12 Mar 2021 06:58:43 +0100 (CET) Received: from mail-pf1-f175.google.com (mail-pf1-f175.google.com [209.85.210.175]) by mails.dpdk.org (Postfix) with ESMTP id D37A61607BD for ; Fri, 12 Mar 2021 06:58:37 +0100 (CET) Received: by mail-pf1-f175.google.com with SMTP id y67so1131601pfb.2 for ; Thu, 11 Mar 2021 21:58:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version; bh=NcIiyYznHmTqJjvCZ1ZHvn2LazvmNPiMRi4aX4wr1WY=; b=UFBl9fiCGxe6gANHbTqgxgFiNkAJNFXNq1p8McGtMfGusCN4lIEb1cxWcT6eBgxjrp gDjKIBSIHldP4fHRHROD/u1q1tSDVS1/tcSlVkTkQbWxTZ0M5sCE2vehpECw7ddt2HTT JkG6n7y2LghwYSGxzCVk/VTqg/7HRxgyw3PRM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version; bh=NcIiyYznHmTqJjvCZ1ZHvn2LazvmNPiMRi4aX4wr1WY=; b=n5WqAta6Q+PfwBzwry3XHkDsJnbVjMlhrKW5pZkxOD4R8zdtlSwnFIdH21+z2YSUQI c0MQmNsyb3eo7YeS1Skf1qiGCWLTHMvYrofCoi9xNOI8cwa1Jd+oWiSZV0+uVUVzAkcs O33/1EXPHX6FRQUmvjq59+Yb7lYm8+ldxxoixUybC/tZx7EmlHzLWQkARnSqEb2hcIYS 1jk9onKOsPd0CUdu/Kg2Sp4f6lTD74vri3kxjUvZ1nRwOZsUTyU5rhwfH8o+zYx//ybX y2RuO+1Mk9S/zKF6KYQbeizhlCou9MQ3PYwO+TkyA0fIzTuQlQTsSmvkOxcTlV1nba2Q 6Urg== X-Gm-Message-State: AOAM531+ZtWNqP+PY1uuo7J2fBkV/f2UyWr/ba8k7DkAmabY7/gyqK1V 1xwuB9lHfO5vxM7y723hgNjn32qcUtO7AKloZXYvHVWBeDpYxH4fXp6A7ydLow9UOL76jZE9qqB zI1dfqVI4Q3AH1C1ylKThodvm3m9jPBoIvRvcNMhYMI17HOrjWwhMTgZR8FLWPv4uUQ== X-Google-Smtp-Source: ABdhPJzVSHVYcX3Z5OKmDCsHoqXD7v4UFPWaiCEIAC3+WZ9EgCoGc6uBw+b7QB+NqssTOJdEt9Aftg== X-Received: by 2002:a63:4808:: with SMTP id v8mr10219638pga.381.1615528716495; Thu, 11 Mar 2021 21:58:36 -0800 (PST) Received: from localhost.localdomain ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id 186sm4413173pfb.143.2021.03.11.21.58.35 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Mar 2021 21:58:36 -0800 (PST) From: Ajit Khaparde To: dev@dpdk.org Cc: ferruh.yigit@intel.com, Kalesh AP , stable@dpdk.org, Somnath Kotur Date: Thu, 11 Mar 2021 21:58:17 -0800 Message-Id: <20210312055819.52789-11-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.21.1 (Apple Git-122.3) In-Reply-To: <20210312055819.52789-1-ajit.khaparde@broadcom.com> References: <20210312055819.52789-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.29 Subject: [dpdk-dev] [PATCH v3 10/12] net/bnxt: fix firmware fatal error handling X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kalesh AP During some fatal firmware error conditions, the PCI config space register 0x2e which normally contains the subsystem ID will become 0xffff. This register will revert back to the normal value after the chip has completed core reset. If we detect this condition, we can poll this config register immediately for the value to revert. Because we use config read cycles to poll this register, there is no possibility of Master Abort if we happen to read it during core reset. This speeds up recovery significantly as we don't have to wait for the conservative min_time before polling to see if the firmware has come out of reset. As soon as this register changes value we can proceed to re-initialize the device. Fixes: df6cd7c1f73a ("net/bnxt: handle reset notify async event from FW") Cc: stable@dpdk.org Signed-off-by: Kalesh AP Reviewed-by: Somnath Kotur Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/bnxt_ethdev.c | 56 ++++++++++++++++++++++++++++++++-- drivers/net/bnxt/bnxt_util.h | 2 ++ 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 9e0ec46403..67ff800da5 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -3743,6 +3743,32 @@ static void bnxt_dev_cleanup(struct bnxt *bp) bnxt_uninit_resources(bp, true); } +static int +bnxt_check_fw_reset_done(struct bnxt *bp) +{ + int timeout = bp->fw_reset_max_msecs; + uint16_t val = 0; + int rc; + + do { + rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); + if (rc < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); + return rc; + } + if (val != 0xffff) + break; + rte_delay_ms(1); + } while (timeout--); + + if (val == 0xffff) { + PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n"); + return -1; + } + + return 0; +} + static int bnxt_restore_vlan_filters(struct bnxt *bp) { struct rte_eth_dev *dev = bp->eth_dev; @@ -3840,6 +3866,13 @@ static void bnxt_dev_recover(void *arg) int rc = 0; pthread_mutex_lock(&bp->err_recovery_lock); + + if (!bp->fw_reset_min_msecs) { + rc = bnxt_check_fw_reset_done(bp); + if (rc) + goto err; + } + /* Clear Error flag so that device re-init should happen */ bp->flags &= ~BNXT_FLAG_FATAL_ERROR; @@ -3891,14 +3924,33 @@ static void bnxt_dev_recover(void *arg) void bnxt_dev_reset_and_resume(void *arg) { struct bnxt *bp = arg; + uint32_t us = US_PER_MS * bp->fw_reset_min_msecs; + uint16_t val = 0; int rc; bnxt_dev_cleanup(bp); bnxt_wait_for_device_shutdown(bp); - rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs, - bnxt_dev_recover, (void *)bp); + /* During some fatal firmware error conditions, the PCI config space + * register 0x2e which normally contains the subsystem ID will become + * 0xffff. This register will revert back to the normal value after + * the chip has completed core reset. If we detect this condition, + * we can poll this config register immediately for the value to revert. + */ + if (bp->flags & BNXT_FLAG_FATAL_ERROR) { + rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); + if (rc < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); + return; + } + if (val == 0xffff) { + bp->fw_reset_min_msecs = 0; + us = 1; + } + } + + rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp); if (rc) PMD_DRV_LOG(ERR, "Error setting recovery alarm"); } diff --git a/drivers/net/bnxt/bnxt_util.h b/drivers/net/bnxt/bnxt_util.h index 8de55e1038..64e97eed15 100644 --- a/drivers/net/bnxt/bnxt_util.h +++ b/drivers/net/bnxt/bnxt_util.h @@ -10,6 +10,8 @@ #define BIT(n) (1UL << (n)) #endif /* BIT */ +#define PCI_SUBSYSTEM_ID_OFFSET 0x2e + int bnxt_check_zero_bytes(const uint8_t *bytes, int len); void bnxt_eth_hw_addr_random(uint8_t *mac_addr);